臺灣博碩士論文加值系統

本論文針對幾種傅立葉演算法去分析比較其算術複雜度，並對不同的架構做硬體效率、硬體成本和速度上的比較分析。最後整合提出一個適用於各種正交分頻多工調變系統的快速傅立業處理器架構，即可變長度單一處理單元架構。其可提供足夠的效能並且可用於所有2n點數的快速傅立業轉換。除此之外，我們亦介紹使用幾種設計技巧可用來簡化硬體複雜度，如：位元長度的模擬、快速傅立業與反快速傅立業處理器的硬體共用、係數暫存器的縮小等等。

In order to design a general efficient FFT/IFFT core suitable for various OFDM communication systems, the thesis first investigates possible design solutions from algorithm level to architecture level. Following that, a variable-length memory-based FFT/IFFT architecture is proposed. The FFT/IFFT core can be applied to all the current OFDM-based FFT computation with sufficient throughput rate. Besides, the thesis also introduces some design methodologies for low hardware complexity realization that include word length simulation, complex multiplier design, ROM table size reduction and hardware sharing of FFT and IFFT, and etc.

Chapter 1 Introduction 1
1.1 Background 1
1.2 Organization of this thesis 3
Chapter 2 Review of FFT Algorithms 4
2.1 Introduction 4
2.2 Basic Concepts of FFT Algorithms 5
2.3 The Fixed-Radix FFT Algorithms 8
2.3.1 Radix-2 FFT Algorithm and Complexity 8
2.3.2 Radix-4 FFT Algorithm and Complexity 12
2.3.3 Radix-8 FFT Algorithm and Complexity 15
2.4 The Split-Radix FFT (SRFFT) Algorithms 18
2.4.1 Split-Radix 2/4 FFT Algorithm and Complexity 19
2.4.2 Split-Radix 2/8 FFT Algorithm and Complexity 21
2.5 Comparisons and Summary 22
Chapter 3 Review of FFT Architectures 24
3.1 Introduction 24
3.2 Pipeline-Based FFT Architectures 25
3.2.1 Introduction 25
3.2.2 Single-Path Delay Feedback Pipeline Architecture 26
3.2.3 Multiple-Path Delay Commutator Pipeline Architecture 32
3.2.4 Comparison of Pipeline Structures 36
3.3 Memory-Based FFT Architectures 39
3.3.1 Introduction 39
3.3.2 Efficient Method for Memory Partition 41
3.3.3 Performance Analysis 42
3.4 Summary 43
Chapter 4 FFT/IFFT Hardware Design for OFDM Communication System 45
4.1 OFDM Basics 45
4.2 FFT/IFFT Hardware Design 47
4.2.1 Algorithm and Architecture Selection 47
4.2.2 Arithmetic Module Design 50
4.2.3 ROM Table Size Reduction 51
4.2.4 Hardware Sharing of FFT and IFFT 53
4.3 Variable-Length FFT Module Design 54
4.4 FFT Outputs Reordering 58
4.5 Summary 60
Chapter 5 Implementation of a VL Memory-Based FFT Architecture 61
5.1 Design Consideration 61
5.2 Complete Architecture 64
5.2.1 Input Buffer and Main Memory 64
5.2.2 Processing Element 65
5.2.3 VL Address Generator (VL_AG) 66
5.2.4 Commutators on Both Sides of The Main Memory Banks 68
5.3 Word Length Optimization 69
5.4 Summary 73
Chapter 6 Conclusion and Future Work 74
6.1 Conclusion 74
6.2 Future Work 74
Bibliography 76

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