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研究生:陳尚志
研究生(外文):Shang-Jr Chen
論文名稱:深次微米與奈米金氧半元件氧化層界面與製程導致元件可靠性的探討
論文名稱(外文):The Investigation of Gate Oxide Interface and Process-Induced Device Reliability in Deep-Submicron and Nanometer CMOS Devices
指導教授:莊紹勳
指導教授(外文):Steve S. Chung
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:118
中文關鍵詞:電荷幫浦法熱載子可靠性問題半導體界面缺陷汲極結構淺溝狀隔離法電漿蝕刻傷害超薄/穿隧氧化層有效通道長度
外文關鍵詞:charge pumping (CP) techniquehot carrier reliabilitysemiconductor interface trapdrain structureshallow-trench-isolationplasma induced damageultra-thin/direct tunneling regime gate oxideeffective channel length
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近年來,電荷幫浦法已被廣泛的應用於分析元件熱載子可靠性問題及半導體界面缺陷。在本論文中,我們將運用此一方法研究深次微米及奈米尺度互補式金氧半元件(CMOS Device)熱載子效應及製程所導致元件可靠性等問題。同時,吾人將開發一套適用於現在及未來奈米級元件界面缺陷分析之新式電荷幫浦技術。
首先,由於次微米(採用LDD結構設計)及深次微米(採用S/D 延伸結構設計)n型元件中,因汲極結構的不同,熱載子效應將會引發不同程度之汲極電流退化。其退化情形將隨著閘氧化層厚度改變及元件汲極結構不同,而呈現不規則的退化情形。迄今,尚無一個適切的方法可以同時解釋發生在這兩個世代的元件可靠性。因此,在本研究中吾人將提出一個新的熱載子可靠性的評測方式,來解釋其元件電流退化的情形。吾人利用有效通道長度中熱載子所產生的界面缺陷(Nit)量,來取代傳統採以基極電流(IB)、衝撞游離化比率((IB/ID)、或是平均/最大界面缺陷((Nit)等為可靠性的指標。經由本研究的驗證,此方法可以準確的評估這兩世代元件熱載子可靠性退化情形。
另一方面,以淺溝狀(STI)隔離法取代區域化氧化隔離法(LOCOS)已成為當代之隔離技術之主流。然而,在採用淺溝狀隔離法的元件技術中,卻發現當通道寬度縮短會造成極其嚴重的可靠性問題。在本研究中,我們以一個新的退化模型及機制來解釋與通道寬度有關之元件退化效應。其中,在n型元件中,吾人提出利用有效界面缺陷(effective Nit)來解釋元件之退化﹔在p型元件中,吾人提出利用通道長度縮短(channel-shortening)效應來解釋元件之退化。這兩種傷害的發生,都與淺溝狀隔離法所導致的機械應力傷害有莫大的關聯。
再者,在電漿蝕刻的過程中,電漿與矽晶圓表面反應,會影響到閘氧化層品質、元件可靠性、及晶圓製作的均勻度,另外,會引發兩種廣為人知的電漿蝕刻傷害- 其一為發生於氧化層及通道區域之電漿充放電傷害﹔另一為發生於閘極邊緣區域之電漿邊緣傷害。本研究則利用電荷幫浦法,來研究電漿蝕刻傷害所增強的熱載子退化現象。同時,吾人提出一個三階段的電漿傷害退化機制,用來解釋發生於n型及p型元件中電漿傷害所增強的退化現象。
最後,製程推進到奈米(sub-100nm)元件世代,元件的設計面臨到諸多物理的極限- 諸如,穿隧電流及量子效應已大到足以影響元件基本電性。這使得奈米元件的電性(尤其是在閘極氧化層品質及元件可靠性)的分析變的越趨困難。在此,吾人開發出一個新的低漏電流電荷幫浦法,它可以分析超小尺寸、超薄氧化層元件中之界面缺陷。即使當閘氧化層厚度微縮到僅僅只有1nm,此法依然可行。而附帶一提的,此法亦可用之於計算奈米元件之有效通道長度,亦可堪稱為目前世界上可合理計算出最小有效通道長度的方法。
簡而言之,本論文成功的利用電荷幫浦法於各種熱載子及製程上所導致元件可靠性問題的探討。同時,亦針對熱載子效應、淺溝狀隔離之機械應力傷害、電漿蝕刻傷害增強的退化進行研究,並提出其元件機制及物理模型。此外,亦針對具穿隧氧化層之奈米元件,提出一個新的低漏電之電荷幫浦法,用來分析超薄氧化層製程品質及其界面缺陷。相信此一新開發之電荷幫浦法,將是分析下一世代奈米元件特性最有效的工具。

The charge pumping (CP) technique has been widely used for the characterization of hot carrier (HC) reliability and the evaluation of semiconductor interface. The objective of this dissertation is to employ this CP technique for investigating the hot carrier induced and process-induced device reliabilities for device dimensions from deep-submicron to nanometer scale. In addition, a more sophisticated CP technique will be developed for the characterization of nanometer CMOS devices.
First of all, since submicron (with LDD) and deep-submicron (with S/D extension) nMOSFET’s have different drain structures, it exhibits different mechanisms of drain current degradation. There exists an ambiguity that drain current degradation depends not only on gate oxide thickness but also on device drain structure. No definite method can provide an adequate solution for these two generations of devices. In this work, a new criterion for HC reliability evaluation has been proposed as a good monitor for the drain current degradation. This monitor uses total values of interface traps generated inside effective channel length, instead of the commonly used substrate current (IB), impact ionization rate (ID/IB), or peak/average values of interface traps. The approach has been successfully demonstrated to be valid for two generations of submicron (with LDD structure) and deep-submicron (with S/D extension structure) nMOSFET’s.
On the other hand, the shallow-trench-isolation (STI) has become the main isolation technique to replace the local oxidation of Si (LOCOS) isolation. While, the STI CMOS devices exhibit severe degradation after hot-carrier stress with a reducing channel width. In this work, new degradation models and mechanisms has been developed to explain the width dependent degradation, in which the effective interface trap generation for nMOSFET’s and channel-shortening length for pMOSFET’s have been used as good monitors. Both HC effects in n- and pMOSFET’s are found to be strongly related to the mechanical stress on the border of the trench.
Furthermore, plasma interaction with the silicon (Si) wafer during the plasma etching process of MOSFET has been known to produce serious damage, which affects the oxide quality, device reliability and wafer uniformity. There are two types of damage induced by plasma etching process- plasma-charging damage generated in the gate oxide and channel region, and plasma edge damage generated near the gate edge. This study will provide a CP profiling technique to evaluate the enhanced HC effect by the plasma-charging. In the mean time, a new three-phase plasma damage mechanism has also been proposed to clarify the enhanced degradation for both n- and pMOSFET’s
Finally, in the era of sub-100nm manufacturing technique, it has reached the fundamental limits for device scaling, such as direct tunneling leakage and quantum effect. This makes the analysis of electrical characteristics in a nano-scaled device more difficult, especially the monitor of oxide quality and the evaluation of device reliability. In this study, we have also developed a new low leakage CP technique for interface trap characterization of very-short dimension and ultra-thin gate oxide devices. Even for a gate oxide thickness down to the 1nm range, this CP technique will still be valid. Moreover, this technique can also be used to calculate the effective channel length in a sub-100nm device, which is the smallest dimension of the length extraction method up-to-date.
In short, this dissertation has successfully employed the CP technique to investigate the hot carrier induced and process-induced device reliabilities. Device mechanism and physical model have been well developed for the studies of the HC effect, the STI induced mechanism stress, and the plasma damage enhanced degradation. Again, a new low leakage CP method has been provided for the sub-100nm device with gate oxide in the range of direct tunneling regime. This newly developed CP technique is believed to be a very powerful tool for the characterization of next generation nanometer CMOS devices.

Contents
Chinese Abstract
English Abstract
Acknowledgements
Contents
Figure Captions
Table Captions
Chapter 1 Introduction
Chapter 2 A New Concept of CP Technique for Gate and S/D Engineering Study of Submicron and Deep-Submicron nMOSFET’s
2.1 Introduction
2.2 Device Fabrication
2.3 Hot-Carrier Reliability for Submicron and Deep-submicron nMOSFET’s
2.3.1 Observation from Experimental Results
2.3.2 Hot-Carrier Reliability for Submicron and Deep-Submicron nMOSFET’s
2.3.2.1 Interface Trap Profiling Technique
2.3.2.2 Hot-Carrier Degradation in n- LDD nMOSFET’s
2.3.2.3 Hot-Carrier Degradation in n+ S/D Extension nMOSFET’s
2.3.2.4 New Criterion for the Evaluation of Hot-Carrier Reliability
2.4 Reliable Gate Engineering Design in Deep-submicron nMOSFET’s
2.5 Summary
Chapter 3 Width Dependent Hot-Carrier Effect in Shallow-Trench-Isolated CMOS Devices
3.1 Introduction
3.2 Device Fabrication
3.3 Results and Discussion
3.3.1 Observations of the Width-Dependent Effect
3.3.2 Physical Model for the STI Enhanced Degradation in nMOSFET
3.3.3 Physical Model for the STI Enhanced Degradation in pMOSFET’s
3.4 Summary
Chapter 4 Plasma-Charging-Enhanced Hot-Carrier Effect and Device Scaling of Deep-Submicron MOSFET’s
4.1 Introduction
4.2 Device Fabrication
4.3 Plasma Damage for Scaled nMOSFET’s
4.3.1 Position Dependence of the Plasma Damage
4.3.2 Antenna Structure Dependence of the Plasma Damage
4.3.3 Channel Length Dependence of the Plasma Damage
4.3.4 A Three-Phase Plasma Damage Mechanism
4.3.5 The Direct Evidence of the Plasma-Charging-Enhanced Edge Damage
4.4 Plasma Damage for Scaled pMOSFET’s
4.5 Summary
Chapter 5 A New CP Methodology to Characterizing the Oxide Quality of Nanometer CMOS Devices with Direct Tunneling Regime Gate Oxide
5.1 Introduction
5.2 Device Preparation
5.3 Results and Discussion
5.3.1 Gate Tunneling Leakage in Charge Pumping Measurement
5.3.2 Set-up of a Low Leakage Charge Pumping Measurement
5.3.3 A New Low Leakage Charge Pumping Methodology
5.3.4 Determination of Interface Traps and Extraction of the Effective Channel Length
5.4 Summary
Chapter 6 Summary and Conclusion
References
Vita
Publication Lists

Chapter 1
[1.1] International Technology Roadmap for Semiconductor (ITRS), Semiconductor Industry, Association, 2001.
[1.2] S.S. Chung, J.-J. Yang, C.-H. Tang and P.-C. Chou, “Characterization of Hot Electron Induced Interface States in LATID MOS Devices Using an Improved Charge Pumping Method,” in Extended Abs. Int’l Solid State Devices and Materials (SSDM), Chiba, Japan, pp. 841-843, 1993.
[1.3] S.S. Chung, and J.-J. Yang, “A New Approach for Characterizing Structure- Dependent Hot-Carrier Effects in Drain-Engineered MOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 46, pp. 1371-1377, 1999.
[1.4] P. Heremans, J. Witters, and G. Groeseneken, and H.E. Maes, “Analysis of the Charge Pumping Technique and its Application for the Evaluation of MOSFET Degradation,” IEEE Trans. on Electron Devices (T-ED), vol. 36, pp. 1318-1335, 1989.
[1.5] A.-S. Grove and D.-J. Fitzgerald, “Suface Effects on p-n Junctions: Characteristics of Surface Space-Charge Regions under Nonequilibrium conditions,” Solid-State Electron, vol. 9 pp. 783, 1966.
[1.6] T. Giebel and K. Goser, “Hot-Carrier Degradation of n-Channel MOSFET’s Characterized by a Gated-Diode Measurement Technique,” IEEE Electron Device Lett. (EDL), vol. 10, pp. 76-78, 1984.
[1.7] P. Sepckbacher, A. Asenov, M. Bollu, F. Koch, and W. Wever, “Hot-Carrier-Induced Deep-Level Defects from Gate-Diode Measurements on MOSFET’s,” IEEE Electron Device Lett. (EDL), vol. 10, pp. 95-97, 1990.
[1.8] C.-Y. Chang, and S.-M. Sze, ULSI Devices, 2000.
[1.9] A. Neugroschel, C.-T. Sah; K.-M. Han, M.-S. Carroll, T. Nishida, J.-T Kavalieros, and Y. Lu, “Direct-Current Measurements of Oxide and Interface Traps on Oxidized Silicon,” IEEE Trans. on Electron Devices (T-ED), vol. 42, pp. 1657-1662, 1995.
[1.10] J. Cai, and C.-T. Sah, “Monitoring Interface Traps by DCIV Method,” IEEE Electron Device Lett. (EDL), vol. 20, pp. 60-63, 1999.
[1.11] A. M. Martirosian, and T.-P. Ma, “Lateral Profiling of Interface Traps and Oxide Charge in MOSFET Devices: Charge Pumping versus DCIV,” IEEE Trans. on Electron Devices (T-ED), vol. 48, pp. 2303-2309, 2001.
[1.12] Y. Toyoshima, H. Iwai, F. Matsuoka, H. Hayashida, K. Maeguchi and K. Kanzaki, “Analysis on Gate-Oxide Thickness Dependence of Hot-Carrier-Induced Degradation in Thin-Gate Oxide nMOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 37, pp. 1496-1503, 1990.
[1.13] S. S. Chung and J. J. Yang, “A New Approach for Characterizing Structure-Dependent Hot-Carrier Effects in Drain-Engineered MOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 46, pp. 1371-1377, 1999.
[1.14] M. Nishigohri, K. Ishimaru, M. Takahashi, Kayama, F. Matsuoka, and M. Kinugawa, “Anomalous Hot-Carrier Induced Degradation in Very Narrow Channel nMOSFET’s with STI Structure,” in IEDM Tech. Digest (IEDM, pp. 881-884, 1996.
[1.15] W. Lee, S. Lee, T. Ahn, and H. Hwang, “Degradation of Hot Carrier Lifetime for Narrow Width MOSFET with Shallow Trench Isolation,” in Proc. of IEEE Int’l Reliability Physics Symp. (IRPS), pp. 259-262, 1999.
[1.16] X.-Y. Li, T. Brozek, P. Aum, D. Chan and C.R. Viswanathan, “Degraded CMOS Hot Carrier Life Time-Role of Plasma Etching Induced Charging Damage and Edge Damage,” in Proc. of IEEE Int’l Reliability Physics Symp. (IRPS), pp. 260-265, 1995.
[1.17] T. Brozek, X.-Y. Li, F. Preuninger, Y.-D. Chan and C.R. Viswanathan, “Assessment of Uniform and Non-uniform Damage in Plasma Etched Submicron Transistor,” in Proc. of Inte’l VLSI Technology, Systems and Applications (VLSI-TSA), pp. 53-56, 1995.
[1.18] S. Krishnan, S. Rangan, S. Hattangady, G. Xing, K. Brennan, M. Rodder and S. Ashok, “Assessment of Charge-Induced Damage to Ultra-thin Gate MOSFETs” in IEDM Tech. Digest (IEDM, pp. 445-448, 1997.
[1.19] H. Shiu, and C. Hu, “Mornitoring Plasma-Process Induced Damage in Thin Oxide,” IEEE Trans. on Semiconductor Manufacturing (T-SM), vol. 6, pp. 96-102, 1993.
[1.20] C.-H. Choi, J.-K. Goo, T.-Y. Oh, Z. Yu, R.W. Dutton, A. Bayoumi, M. Cao, P.V. Voorde, and D. Vook, “C-V and Gate Tunneling Current Characterization of Ultra-thin Gate Oxide MOS (tox = 1.3-1.8nm),” in Symp. on VLSI Tech. Dig. (VLSI), pp. 63-64, 1999.
[1.21] K. Yang, Y.-C. King, and C. Hu, “Quantum Effect in Oxide Thickness Determination from Capacitance Measurement,” in Symp. on VLSI Tech. Dig. (VLSI), pp. 77-78, 1999.
Chapter 2
[2.1] C. Hu, S.-C. Tam, F.-C. Hsu, P.-K. Ko, and T.Y. Chan, and K.-W. Terril, “Hot-Electron-Induced MOSFET Degradation- Model, Monitor, and Improvement,” IEEE Trans. on Electron Devices (T-ED), vol. 32, pp. 375-385, 1985.
[2.2] Y. Toyoshima, H. Iwai, F. Matsuoka, H. Hayashida, K. Maeguchi and K. Kanzaki, “Analysis on Gate-Oxide Thickness Dependence of Hot-Carrier-Induced Degradation in Thin-Gate Oxide nMOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 37, pp. 1496-1503, 1990.
[2.3] S. S. Chung and J. J. Yang, “A New Approach for Characterizing Structure-Dependent Hot-Carrier Effects in Drain-Engineered MOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 46, pp. 1371-1377, 1999.
[2.4] S. C. Sun, and J. D. Plummer, “Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces,” IEEE Trans. on Electron Devices (T-ED), vol. 27, pp. 1497-1508, 1980.
[2.5] T. Hori, J. Hirase, Y. Odake, and Y. Tasui, “Deep-Submicron Large-Angle-Tilt Implanted Drain (LATID) Technology,” IEEE Trans. on Electron Devices (T-ED), vol. 39, pp. 2312, 1992.
[2.6] S.S. Chung, J.-J. Yang, C.-H. Tang and P.-C. Chou, “Characterization of Hot Electron Induced Interface States in LATID MOS Devices Using an Improved Charge Pumping Method,” in Extended Abs. Int’l Solid State Devices and Materials (SSDM), Chiba, Japan, pp. 841-843, 1993.
[2.7] S.-M. Cheng, C.-M. Yih, J.-C. Yeh, S.-N. Kuo, and S.S. Chung, “A Unified Approach to Profiling the Lateral Distributions of Both Oxide Charge and Interface States in n-MOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 44, pp. 1908-1914, 1997.
[2.8] F. C. Hsu, and H. R. Grinolds, “Structure-Enhanced MOSFET Degradation Due to Hot-Electron Injection” IEEE Electron Device Lett. (EDL), vol. 5, pp. 71-73, 1984.
[2.9] G. J. Hu, C. Chang, and Y. T. Chia, “Gate-Voltage-Dependent Effective Channel Length and Series Resistance of LDD MOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 34, pp. 2469-2475, 1987.
Chapter 3
[3.1] M. Nishigohri, K. Ishimaru, M. Takahashi, Kayama, F. Matsuoka, and M. Kinugawa, “Anomalous Hot-Carrier Induced Degradation in Very Narrow Channel nMOSFET’s with STI Structure,” in IEDM Tech. Digest (IEDM, pp. 881-884, 1996.
[3.2] W. Lee, S. Lee, T. Ahn, and H. Hwang, “Degradation of Hot Carrier Lifetime for Narrow Width MOSFET with Shallow Trench Isolation,” in Proc. of IEEE Int’l Reliability Physics Symp. (IRPS), pp. 259-262, 1999.
[3.3] J.-F. Chen, K. Ishimaru, and C. Hu, “Enhanced Hot-Carrier Induced Degradation in Shallow Trench Isolation Narrow Channel PMOSFET’s” IEEE Electron Device Lett. (EDL), vol. 19, pp. 332-334, 1998.
[3.4] R. Woltjer, G.M. Paulzen, H. Lifka, and P. Woerlee, “Positive oxide-charge generation during 0.25mm PMOSFET hot-carrier degradation,” IEEE Electron Device Lett. (EDL), vol. 15, pp. 427-429, 1994.
[3.5] B.-S. Doyle, K.-R. Mistry, and D.-B. Jackson, “Examination of Gradual-Junction p-MOS Structure for Hot Carrier Control Using a New Lifetime Extraction Method,” IEEE Trans. on Electron Devices (T-ED), vol. 39, pp. 2290-2297, 1992.
[3.6] B.-S. Doyle, and K.-R. Mistry, “Anomalous Hot-Carrier Behavior for LDD p-channel Transistors,” IEEE Electron Device Lett. (EDL), vol. 14, pp. 536-538, 1993.
[3.7] F. Matsuoka, H. Iwai, H. Hayashida, K. Hama, Y. Toyoshima, and K.Maeguchi, “Analysis of Hot-Carrier-Induced Degradation Mode on pMOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 37, pp. 1487-1495, 1990.
Chapter 4
[4.1] X.-Y. Li, T. Brozek, P. Aum, D. Chan and C.R. Viswanathan, “Degraded CMOS Hot Carrier Life Time-Role of Plasma Etching Induced Charging Damage and Edge Damage,” in Proc. of IEEE Int’l Reliability Physics Symp. (IRPS), pp. 260-265, 1995.
[4.2] T. Brozek, X.-Y. Li, F. Preuninger, Y.-D. Chan and C.R. Viswanathan, “Assessment of Uniform and Non-uniform Damage in Plasma Etched Submicron Transistor,” in Proc. of Inte’l VLSI Technology, Systems and Applications (VLSI-TSA), pp. 53-56, 1995.
[4.3] S. Krishnan, S. Rangan, S. Hattangady, G. Xing, K. Brennan, M. Rodder and S. Ashok, “Assessment of Charge-Induced Damage to Ultra-thin Gate MOSFETs” in IEDM Tech. Digest (IEDM, pp. 445-448, 1997.
[4.4] H. Shiu, and C. Hu, “Mornitoring Plasma-Process Induced Damage in Thin Oxide,” IEEE Trans. on Semiconductor Manufacturing (T-SM), vol. 6, pp. 96-102, 1993.
[4.5] Z.-J. Ma, H. Shin, P.-K. Ko, and C. Hu, “Effect of Plasma Charging Damage on the Noise Performance of Thin-Oxide MOSFET’s,” IEEE Electron Device Lett. (EDL), vol. 15, pp. 224-226, 1994.
[4.6] T. Gu, M. Okandan, O. O. Awadelkarim, S. J. Fonash, J. F. Rembetski, P. Aum and Y. D. Chan, “Impact of polysilicon dry etching on 0.5mm NMOS Transistor Performance: The Presence of Both Plasma Bombardment Damage and Plasma Charging Damage,” IEEE Electron Device Lett. (EDL), vol. 15, pp. 48-50, 1994.
[4.7] M.G. El Hassan, O.O. Awadelkarim and J.D. Werking, “The Impact of Metal-1 Plasma Processing-Induced Hot Carrier Injection on the Characteristics and Reliability of n-MOSFETs,” IEEE Trans. on Electron Devices (T-ED), vol. 45, pp. 861-866, 1998.
[4.8] T. Brozek, V. R. Rao, A. Sridharan, J. D. Werking, Y. D. Chan, and C. R. Viswanathan, “Charge Injection Using Gate-Induced-Drain-Leakage Current for Characterization of Plasma Edge Damage in CMOS Devices” IEEE Trans. on Semiconductor Manufacturing (T-SM), vol. 11, pp. 211-216, 1998.
[4.9] K. R. Mistry, B. J. Fishbein, and B. S. Doyle, “Effect of Plasma-Induced Charging Damage on n-Channel and p-Channel MOSFET Hot Carrier Reliability,” in Proc. of IEEE Int’l Reliability Physics Symp. (IRPS), pp. 42-47, 1994.
[4.10] S.S. Chung, J.-J. Yang, C.-H. Tang and P.-C. Chou, “Characterization of Hot Electron Induced Interface States in LATID MOS Devices Using an Improved Charge Pumping Method,” in Extended Abs. Int’l Solid State Devices and Materials (SSDM), Chiba, Japan, pp. 841-843, 1993.
[4.11] S. S. Chung and J. J. Yang, “A New Approach for Characterizing Structure-Dependent Hot-Carrier Effects in Drain-Engineered MOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 46, pp. 1371-1377, 1999.
[4.12] C. Chen and T. P. Ma, “Direct Lateral Profiling of Hot-Carrier-Induced Oxide Charge and Interface Traps in Thin Gate MOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 45, pp. 512-520, 1998.
[4.13] K. Hashimoto, “New Phenomena of Charge Damage in Plasma Etching: Heavy Damage Only through Dense-Line Antenna,” Jpn. J. Appl. Phys. (JJAP), vol. 32, pp. 6109-6113, 1993.
[4.14] K. Hashimoto, “Charge Damage Caused by Electron Shading Effect,” Jpn. J. Appl. Phys. (JJAP), vol. 33, pp. 6013-6018, 1994.
Chapter 5
[5.1] L.-K. Han, C.-W. Yoon, J. Kim, J. Yan, and D.-L. Kwong, “Formation of High Quality Ultrathin Oxide/Nitride (ON) Stacked Capacitors by in-Situ Multiple Rapid Thermal Processing [DRAM cells],” IEEE Electron Device Lett. (EDL), Vol. 16, pp. 348-350, 1995.
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[5.7] S.-F. Ting, Y.-K. Fang, C.-H. Chen, C.-W. Yang, W.-T. Hsieh, J.-J. Ho, M.-C. Yu, S.-M. Jang, C.-H. Yu, M.-S. Liang, S. Chen, and R. Shih, “The Effect of Remote Plasma Nitridation on the Integrity of the Ultrathin Gate Dielectric Films in 0.13 mm CMOS Technology and Beyond,” IEEE Electron Device Lett. (EDL), vol. 22, pp. 327-329, 2001.
[5.8] C.-H. Chen, Y.-K. Fang, C.-W. Yang, S.-F. Ting, Y.-S. Tsair, M.-F. Wang, Y.-M. Lin, M.-C. Yu, S.-C. Chen, C.-H. Yu, and M.-S. Liang, “High-Quality Ultrathin (1.6 nm) Nitride/Oxide Stack Gate Dielectrics Prepared by Combining Remote Plasma Nitridation and LPCVD Technologies,” IEEE Electron Device Lett. (EDL), vol. 22, pp. 260-262, 2001.
[5.9] G. Dundar, and K. Rose, “Comparing Models for the Growth of Silicon-Rich Oxides (SRO),” IEEE Trans. on Semiconductor Manufacturing (T-SM), vol. 9, pp. 74-81, 1996.
[5.10] C. Jiang, C. Hu, C.-H. Chen, and P.-N. Tseng, “Impact of Inter-Metal-Oxide Deposition Condition on NMOS and PMOS Transistor Hot Carrier Effect,” in Proc. of IEEE Int’l Reliability Physics Symp. (IRPS), pp. 122-126, 1992.
[5.11] K.-T. Chang, and K. Rose, “Dominance of Interface Effects in SRO-SiO2-SRO DEIS Structures for EAROMs,” IEEE Trans. on Electron Devices (T-ED), vol. 35, pp. 1645-1650, 1988.
[5.12] C.-H. Choi, J.-K. Goo, T.-Y. Oh, Z. Yu, R.W. Dutton, A. Bayoumi, M. Cao, P.V. Voorde, and D. Vook, “C-V and Gate Tunneling Current Characterization of Ultra-thin Gate Oxide MOS (tox = 1.3-1.8nm),” in Symp. on VLSI Tech. Dig. (VLSI), pp. 63-64, 1999.
[5.13] K. Yang, Y.-C. King, and C. Hu, “Quantum Effect in Oxide Thickness Determination from Capacitance Measurement,” in Symp. on VLSI Tech. Dig. (VLSI), pp. 77-78, 1999.
[5.14] Lewis M. Terman, Solid-State Electronics, Vol. 5(5), p. 285-299, 1962.
[5.15] S.S. Chung, J.-J. Yang, C.-H. Tang and P.-C. Chou, “Characterization of Hot Electron Induced Interface States in LATID MOS Devices Using an Improved Charge Pumping Method,” in Extended Abs. Int’l Solid State Devices and Materials (SSDM), Chiba, Japan, pp. 841-843, 1993.
[5.16] S.S. Chung, and J.-J. Yang, “A New Approach for Characterizing Structure- Dependent Hot-Carrier Effects in Drain-Engineered MOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 46, pp. 1371-1377, 1999.
[5.17] P. Heremans, J. Witters, and G. Groeseneken, and H.E. Maes, “Analysis of the Charge Pumping Technique and its Application for the Evaluation of MOSFET Degradation,” IEEE Trans. on Electron Devices (T-ED), vol. 36, pp. 1318-1335, 1989.
[5.18] C. Chen, and T.-P. Ma, “Direct Lateral Profiling of Hot-Carrier-Induced Oxide Charge and Interface Traps in Thin Gate MOSFET’s,” IEEE Trans. on Electron Devices (T-ED), vol. 45, No. 2, pp. 512-519, 1998.
[5.19] P. Masson, J.-L. Autran, and J. Brini, “On the Tunneling Component of Charge Pumping Current in Ultrathin Gate Oxide MOSFETs,” IEEE Electron Device Lett. (EDL), Vol. 20, pp. 92-94, 1999.

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