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研究生:王錦焜
研究生(外文):Chin-Kun Wang
論文名稱:極大型積體電路平坦化及多層金屬化之研究
論文名稱(外文):Planarization and Metallization for Multilevel Interconnect Application in Ultra Large Scale Integrated Circuits
指導教授:鄭晃忠鄭晃忠引用關係
指導教授(外文):Huang-Chung Cheng
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:184
中文關鍵詞:平坦化多層金屬化極大型積體電路
外文關鍵詞:Multilevel InterconnectPlanarizationMetallization
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摘要
當極大型積體電路在功能複雜度上增加及效能速度上提升時,使得積體電路不只在元件尺寸上需要積極的縮小,而且對於先進的多層金屬導線技術有著迫切的需求。隨著製程技術的進步,極大型積體電路的金屬導線不單是線寬及線距急遽的縮小,在層數上也有顯著的增加。特別是當製程技術到達0.25 微米或更先進時,來自金屬導線的RC遲延(RC Delay)甚至超越電晶體元件的RC 效應,變成影響積體電路速度及效能的主要因素。這種現象使得許許多多新的多層金屬化製程模組技術的開發,在不影響量產性、高良率、高可靠度的前提下,更著重在導線電容及電阻的降低。在此篇論文中,針對不同技術世代的極大型積體電路之平坦化及多層金屬化製程進行系統性的研究。
隨著技術演進,不同的製程架構經常被選擇來滿足不同技術世代的需求。在此研究中,數個具有高度可能性應用於不同技術世代的量產之平坦化及多層金屬化製程被詳細的探討,並且著重在製程整合及可靠度的了解。
針對極大型積體電路多層金屬導線平坦化的要求,在0.35微米世代中,SOG因與氧氣電漿反應,造成材料物性退化的機構被詳細的探究,進而導入一種改良的SOG技術。在0.25 微米及以下的世代,一種藉由電子迴旋共振(ECR)產生高密度電漿(HDP)的氧化物沉積技術被有效的發展出來。其完整的探討範圍包含了個別製程模組的分析,與化學機械研磨(CMP)技術的整合,多層金屬化的驗證,製程引起元件損傷之機制及避免元件可靠度損傷的對策。接著是具有低介電常數(Low-K)的氟化玻璃(FSG)用於銅導線鑲埋(Damascene)技術的整合性探討,提供0.13 微米及以下世代在多層金屬化下RC遲延及訊號交互干擾的效應上有效的降低。最後,藉由一種用於護層的高品質及可紫外光穿透的氮化矽(SiN)薄膜之成功開發作為結尾。
在多層金屬化方面,一種具有低電阻率及高覆蓋率(Step Coverage)的有機金屬氣相沉積(MOCVD)之TiN:C薄膜被有效開發並應用於0.25 微米及以下世代之擴散障礙層。導入於製程整合的鎢栓塞(W plug)多層金屬導線應用也得到良好的結果驗證。此外,也成功整合這個改良的TiN:C薄膜及一種強化的低介電常數(Low-K)之迴旋塗佈高分子(Spin-on-Polymer)製程,並在平坦化及多層金屬化應用上獲致確認。為了0.18 微米及以下世代之產品良率的改善及可靠度的提升,一種對於WCMP技術的整合分析手法被提出,不僅對於WCMP模組技術本身進行探討,也對WCMP後續的製程技術進行分析,以期能符合晶圓代工所面臨的產品多樣性的嚴苛挑戰。
最後,參考國際半導體技術藍圖(ITRS)年報中所載的極大型積體電路平坦化及多層金屬化技術趨勢,針對未來可以研究的方向提出一些自己的淺見。

Abstract
With the increased complexity and faster performances of ultra large scale integrated (ULSI) circuits, not only the device geometry is aggressively driven but also the advanced multilevel interconnect technology is eagerly required. Following technology evolution, ULSI circuits have led to a significant reduction in interconnect pitch and a dramatic increase in the number of metal layers for wiring. Especially in sub-quarter micron technology and beyond, the RC delay from interconnect instead of transistor is becoming the dominant factor for circuit performances. This phenomenon leads to a variety of new process module development which aim at the robust multilevel interconnect with reducing capacitance and resistance; meanwhile no sacrifice on manufacturability, high yield and high reliability. In this thesis, the systematical investigations on planarization and metallization for multilevel interconnect application in ULSI circuits were discussed.
Through technology evolution, different process schemes are chosen to serve the requirements of different technology generations. In this study, several planarization and metallization processes with high potential for production implementation of migrated technology generations are introduced, and the process characterizations with integration and reliability viewpoints are focused.
In serving inter-metal-dielectric (IMD) planarization requirements for multilevel interconnect application in ULSI circuits, the degradation mechanism of siloxane spin-on-glass (SOG) damaged by oxygen plasma as well as a modified siloxane SOG process were investigated in details for achieving robust via integrity in 0.35um technology. The high density plasma chemical vapor deposition (HDP CVD) process using electron cyclotron resonance (ECR) source was well developed to fulfill the IMD criteria in 0.25um technology and beyond. The comprehensive study covers individual module characterization, process integration with oxide CMP, robust via-plug demonstration, process induced device degradation and the solutions with reliability validation. The following is an integrated characterization of high quality low-K FSG films for Cu dual-damascene application to offer the reduced RC delay and signal cross-talk in 0.13um technology and beyond; finally completed by the successful development of a high quality and UV-transparent SiNx for passivation application.
In terms of multilevel interconnect metallization, an enhanced MOCVD TiN:C film with low resistivity and excellent step-coverage was developed for barrier layer application in sub-quarter micron technology. Robust W via-plug integrity was confirmed. Successful integration of the enhanced MOCVD TiN:C film and a modified low-K spin-on-polymer was conducted as well. Aiming at the yield improvement and reliability enhancement for 0.18um technology and beyond, an integrated WCMP process characterization which includes both WCMP individual modules as well as sequential integrated process steps were well performed to serve the stringent requirements in ASIC foundry facility. Finally, referring to the interconnect technology roadmap summarized in ITRS (International Technology Roadmap for Semiconductor) annual report, some suggestions on future research orientation were proposed.

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Outline 2
Chapter 2 A Modified Siloxane SOG Process for Inter-metal-
planarization 4
2.1 Introduction 4
2.2 Experimental 4
2.3 Results and Discussion 5
2.4 Summary 8
Chapter 3 Investigation of the High Density Plasma CVD Process
Integrated with Oxide CMP for Inter-metal-
planarization 21
3.1 Introduction 21
3.2 Experimental 21
3.3 Results and Discussion 22
3.4 Summary 25
Chapter 4 Control of Process Induced Device Damage During High
Density Plasma Oxide Deposition 41
4.1 Introduction 41
4.2 Experimental 41
4.3 Results and Discussion 42
4.4 Summary 48
Chapter 5 Integrated Process Characterization of Fluorinated
Silicate Glass (FSG) Films for Dual-damascene Cu
Interconnect 59
5.1 Introduction 59
5.2 Experimental 60
5.3 Results and Discussion 61
5.4 Summary 66
Chapter 6 Investigation of A High Quality and UV-transparent
PECVD SiNx Film for Passivation Application in ULSI
Circuits 82
6.1 Introduction 82
6.2 Experimental 83
6.3 Results and Discussion 84
6.4 Application to EPROM Devices 87
6.5 Summary 88
Chapter 7 An Enhanced MOCVD TiN:C Film for Barrier Metal
Application 104
7.1 Introduction 104
7.2 Experimental 105
7.3 Results and Discussion 106
7.4 Summary 109
Chapter 8 Integration of An Enhanced MOCVD TiN:C and Low-K
Spin-on-polymer for Via-plug Application 126
8.1 Introduction 126
8.2 Experimental 127
8.3 Results and Discussion 128
8.4 Summary 131
Chapter 9 Integrated WCMP Characterization for Via-plug
Application in ULSI Circuits 143
9.1 Introduction 143
9.2 Experimental 144
9.3 Results and Discussion 145
9.4 Summary 149
Chapter 10 Conclusions and Suggestions 161
10.1 Conclusions of This Thesis 161
10.2 Suggestions for Future Work 165
References 171
Vita 180
Publication List 181

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