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研究生:王志豪
研究生(外文):Chih-Hao Wang
論文名稱:研究及控制離子佈植產生缺陷所引發之異常擴散在0.13微米及以下元件設計上的應用
論文名稱(外文):Investigation and Control of Implantation Damage Induced Anomalous Diffusion in 0.13mm and beyond CMOS Device Design
指導教授:汪大暉
指導教授(外文):Tahui wang
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
中文關鍵詞:離子佈植缺陷擴散元件
外文關鍵詞:ImplantationDamageDiffusiondevice
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離子佈植產生缺陷所引發之離子異常擴散已在深次微米元件技術領域中引起廣泛討論。本篇論文將針對離子異常擴散在0.13微米及以下元件設計應用進行研究。
首先,吾人發現在p型金氧半場效電晶體中,介面導致硼離子反向(uphill)擴散是主要影響p型接面深度的原因。針對極低能量的離子佈植調查低溫製程時硼離子反向擴散對p型金氧半場效電晶體的影響,二次離子質譜儀的分析結果顯示在源極集極延伸(source/drain extension)工程中硼離子介面堆積是非常重要的,利用反向(uphill)擴散可以顯著改善p型金氧半場效電晶體的短通道效應及飽和電流-漏電流(Idsat-Ioff)特性。對極低能量的離子佈植而言,硼離子暫態加強擴散(Transient Enhanced Diffusion)是不重要的,我們發現利用加入一個快速熱回火製程來降低暫態加強擴散的做法反而是對元件特性有害的。我們探索硼離子反向擴散與溫度的關係,我們觀察到硼離子反向擴散只發生在一定的溫度範圍,低溫製程(< 600C)對硼離子極淺接面的形成是有害的,另一方面,相對高溫製程(>700C)反而能讓硼離子反向擴散的好處發揮到最大的效果。
其次,吾人提出一個創新製程,其中利用銻離子援助砷離子源極集極延伸來為低於0.1微米n型金氧半場效電晶體產生一個陡峭(steep)且反梯度(retrograde)的銦離子口袋(pocket)分佈。根據吾人研究的結果發現,藉由影響銦離子佈植所產生的非晶格層中缺陷的分佈,這一新製程可以在相同的元件漏電流之下改善元件8%的飽和電流,也可以降低100倍以上n型電晶體接面漏電流和降低14%靠近閘極的接面側面電容。我們對此一新製程所製造的元件作可靠性分析,結果顯示在熱載子效應 (Hot Carrier Effects) 上有明顯的改善且對閘極氧化層的品質上沒有影響。
最後,吾人利用磷離子暫態加強擴散特性來最佳化輕摻雜集極(LDD)的摻雜分佈,藉此改善3.3V輸入輸出元件的熱載子效應。我們針對砷磷輕摻雜集極的n型金氧半場效電晶體,在有無磷離子暫態加強擴散的情形下,對熱載子效應作完整的分析。結果顯示有磷離子暫態加強擴散的n型金氧半場效電晶體,其基版(substrate)電流比沒有磷離子暫態加強擴散的n型金氧半場效電晶體降低很多,原因是因為暫態加強擴散可以產生一個更傾斜(graded)的輕摻雜集極的摻雜分佈,因此形成了一個較低的側向電場。我們可以藉由最佳化砷離子佈植能量來進一步改善熱載子效應。針對暫態加強擴散的影響作二次離子質譜儀的分析,和二維電場及電流分佈的元件模擬。砷離子暫態加強擴散對元件飽和電流和漏電流的影響也一起作了完整的調查。

This dissertation addresses the investigation and control of implantation damage induced anomalous diffusion in CMOS device design.
First, interface induced boron uphill diffusion was found to play a major role in determining the junction depth of S/D extensions in a pMOSFET. The effects of the boron up-hill diffusion during low temperature thermal cycles were investigated in ultra-low energy BF2 implanted pMOS devices. Results of secondary ion mass spectrometry (SIMS) analysis show that boron interface pile-up is very important in S/D extension engineering. Short channel effects and Idsat-Ioff characteristics in pMOSFETs can be significantly improved by utilizing the up-hill diffusion. Transient enhanced diffusion (TED) of boron is found to be unimportant due to ultra-low implant energy. Attempts to reduce TED by inclusion of extra RTA are shown to be detrimental to device characteristics. Dependence of the boron up-hill diffusion on temperature was explored. It was observed that the uphill diffusion occurs only in a certain range of temperature. Low temperature process (<600C) is deleterious to boron ultra-shallow junction formation. Instead, relatively high temperature process, 700°C, is necessary to take maximum advantage of the uphill diffusion effect.
Next, we propose a novel process whereby Antimony Assisted Arsenic Source/Drain Extension (A3 SDE) is employed to realize a steep and retrograde indium pocket profile for sub-0.1mm nMOSFETs. By engineering the defect distributions in the amorphous layer created by indium implant, this new process improves 8% current drive while maintaining the same Ioff. It reduces nMOS diode leakage by two orders of magnitude and sidewall junction capacitance near the gate by 14%. Reliability assessment of devices fabricated by the A3 SDE process reveals significant improvement in hot carrier effects and no observable degradation of gate oxide integrity.
Finally, Optimization of a LDD doping profile to enhance hot carrier resistance in 3.3V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFETs with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced, as compared to the one without TED. The reason is that the TED effect can yield a more graded n- LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional device simulation for electric field and current flow distributions have been conducted. The phosphorus TED effects on transistor driving current and off-state leakage current are also investigated.

Chapter 1 Introduction 1
Chapter 2 Ultra-Shallow Junction Formation in pMOSFETs
via Interface Induced Boron Up-Hill Diffusion: Temperature Effect and Application 10
2.1 Introduction 10
2.2 Interface Induced Up-Hill Diffusion of Boron 14
2.3 Device Results of Up-Hill Diffusion 22
2.4 Temperature Effect and Device Results 25
2.5 Summary 30
Chapter 3 Antimony Assisted Arsenic S/D Extension (A3 SDE) Engineering for Sub-0.1mm nMOSFETS: A Novel
Approach to Steep and Retrograde Indium Pocket
Profiles 33
3.1 Introduction 33
3.2 Device Fabrication 40
3.3 SIMS and XTEM Analysis 40
3.4 Device Characteristics 48
3.5 Reliability Assessment 58
3.6 Summary 62
Chapter 4 Arsenic/Phosphorus LDD Optimization by Taking
Advantage of Phosphorus Transient Enhanced Diffusion
for High Voltage Input/Output CMOS Devices 66
4.1 Introduction 66
4.2 Device Fabrication 70
4.3 Results & Discussions 71
4.3.1 Effects of Phosphorus TED 71
4.4.2 Optimization of Arsenic Implant 84
4.4 Effect of Low Thermal Budget Spacer Process 90
4.5 Summary 93
Chapter 5 Conclusions 94

Chapter 1
[1.1] International Technology Roadmap for Semiconductors (Semiconductor Industry Association), 2001.
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[1.3] Aditya Agarwal, D. J. Eaglesham, H. -J. Gossmann, L. Pelaz, S. B. Herner, D. C. Jacobson, T. E. Haynes, Y. Erokhin, and R. Simonton, “Boron-Enhanced-Diffusion of Boron: The Limiting Factor for Ultra-Shallow Junctions”, in IEDM Tech. Dig., pp.467-470, 1997.
[1.4] Scott T. Dunham, Srinivasan Chakravarthi, and Alp H. Gencer, “Beyond TED: Understanding Boron Shallow Junction Formation”, in IEDM Tech. Dig., pp.501-504, 1998.
[1.5] H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, and T. Kunio, ൵-nm Gate Length CMOS Technology and Beyond using Steep Halo," in IEDM Tech. Dig., pp.49-52, 2000.
[1.6] H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, and T. Kunio, "Sub-50-nm Physical Gate Length CMOS Technology and Beyond Using Steep Halo," IEEE Trans. Electron Devices., Vol. 49, NO. 1, pp.89-95, 2002.
[1.7] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling Challenges and Device Design Requirements for High Performance Sub-50nm Gate Length Planar CMOS Transistors," in Symp. VLSI Tech., pp.174-175, 2000.
[1.8] M. Rodder, S. Aur, and I.-C. Chen, “A Scaled 1.8V, 0.18mm Gate Length CMOS Technology: Device Design and Reliability Considerations,” in IEDM Tech. Dig., pp.415-418, 1995.
[1.9] K. Miyashita, et al., "Optimized Halo Structure for 80 nm Physical Gate CMOS Technology with Indium and Antimony Highly Angled Ion Implantation," in IEDM Tech. Dig., pp.645-648, 1999.
[1.10] N. Bhat, P. Chen, et al., "Hot carrier reliability consideration in the integration of dual gate oxide transistor process on a sub-0.25m CMOS technology for embedded application," in IEDM Tech. Dig., pp.427-430, 1999.
Chapter 2
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[2.12] A. E. Michel, W. Rausch, P. A. Ronsheim, and R. H. Kastl, "Rapid Annealing and the Anomalous Diffusion of Ion Implanted Boron into Silicon," Appl. Phys. Lett., Vol. 50, No. 7, pp.416-418, 1987.
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[2.21] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling Challenges and Device Design Requirements for High Performance Sub-50nm Gate Length Planar CMOS Transistors," in Symp. VLSI Tech., pp.174-175, 2000.
[2.22] K.K. Young, S.Y. Wu, C.C. Wu, C.H. Wang, C.T. Lin, J.Y. Cheng, M. Chiang, S.H. Chen, T.C. Lo, Y.S. Chen, J.H. Chen, L.J. Chen, S.Y. Hou, J.J. Liaw, T.E. Chang, C.S. Hou, J. Shih, S.M. Jeng, H.C. Hsieh, Y. Ku, T. Yen, H. Tao, L. C. Chao, S. Shue, S.M. Jang, T.C. Ong, C.H. Yu, M.S. Liang, C.H. Diaz, J.Y.C. Sun, “A 0.13mm CMOS Technology with 193nm Lithography and Cu/Low-k for High Performance Applications,” in IEDM Tech. Dig., pp. 563-566, 2000.
Chapter 3
[3.1] Y. Taur and E. J. Nowak, "CMOS Devices below 0.1mm: How High Will Performance Go?" in IEDM Tech. Dig., pp.215-218, 1997.
[3.2] Y. Taur, C. H. Wann, and D. J. Frank, ൡnm CMOS Design Considerations" in IEDM Tech. Dig., pp.789-792, 1998.
[3.3] H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, and T. Kunio, ൵-nm Gate Length CMOS Technology and Beyond using Steep Halo," in IEDM Tech. Dig., pp.49-52, 2000.
[3.4] H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, and T. Kunio, "Sub-50-nm Physical Gate Length CMOS Technology and Beyond Using Steep Halo," IEEE Trans. Electron Devices., Vol. 49, NO. 1, pp.89-95, 2002.
[3.5] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling Challenges and Device Design Requirements for High Performance Sub-50nm Gate Length Planar CMOS Transistors," in Symp. VLSI Tech., pp.174-175, 2000.
[3.6] D. L. Kendall and D. B. DeVries, in Semiconductor Silicon 1969, edited by R. R. Haberect and E. L. Kern (Electrochemical Society, New York, 1969).
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[3.15] K. Miyashita, H. Yoshimura, M. Takayanagi, M. Fujiwara, K. Adachi, T, Nakayama, and Y. Toyoshima, "Optimized Halo Structure for 80 nm Physical Gate CMOS Technology with Indium and Antimony Highly Angled Ion Implantation," in IEDM Tech. Dig., pp.645-648, 1999.
[3.16] K.K. Young, S.Y. Wu, C.C. Wu, C.H. Wang, C.T. Lin, J.Y. Cheng, M. Chiang, S.H. Chen, T.C. Lo, Y.S. Chen, J.H. Chen, L.J. Chen, S.Y. Hou, J.J. Liaw, T.E. Chang, C.S. Hou, J. Shih, S.M. Jeng, H.C. Hsieh, Y. Ku, T. Yen, H. Tao, L. C. Chao, S. Shue, S.M. Jang, T.C. Ong, C.H. Yu, M.S. Liang, C.H. Diaz, J.Y.C. Sun, “A 0.13mm CMOS Technology with 193nm Lithography and Cu/Low-k for High Performance Applications,” in IEDM Tech. Dig., pp.563-566, 2000.
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Chapter 4
[4.1] M. Rodder, S. Aur, and I.-C. Chen, “A Scaled 1.8V, 0.18mm Gate Length CMOS Technology: Device Design and Reliability Considerations,” in IEDM Tech. Dig., pp.415-418, 1995.
[4.2] H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, and T. Kunio, ൵-nm Gate Length CMOS Technology and Beyond using Steep Halo," in IEDM Tech. Dig., pp.49-52, 2000.
[4.3] K. Miyashita, H. Yoshimura, M. Takayanagi, M. Fujiwara, K. Adachi, T. Nakayama, and Y. Toyoshima, "Optimized Halo Structure for 80 nm Physical Gate CMOS Technology with Indium and Antimony Highly Angled Ion Implantation," in IEDM Tech. Dig., pp.645-648, 1999.
[4.4] N. Bhat, P. Chen, P. Tsui, A. Das, M. Foisy, Y. Shiho, J. Higman, J-Y Nguyen, S. Gonzales, S. Collins, and D. Workman. "Hot carrier reliability consideration in the integration of dual gate oxide transistor process on a sub-0.25m CMOS technology for embedded application," in IEDM Tech. Dig., pp.427-430, 1999.
[4.5] D. K. Nayak, M. Y. Hao, J. Umali, and R. Rakkhit, “A Comprehensive Study of Performance and Reliability of P, As, and Hybrid As/P nLDD Junctions for Deep-Submicron CMOS Logic Technology,” IEEE Electron Device Lett. Vol. 18, No. 6, pp.281-283, 1997.
[4.6] A. E. Michel, W. Rausch, P. A. Ronsheim, and R. H. Kastl, " Rapid annealing and anomalous diffusion of ion implanted boron into silicon," Appl. Phys. Lett., Vol. 50, No. 7, pp.416-418, 1987.
[4.7] Shaofeng S. Yu, Harold W. Kennel, Martin D. Giles, and Paul A. Packan, “Simulation of Transient Enhanced Diffusion Using Computationally Efficient Models,” in IEDM Tech. Dig., pp.509-512, 1997.
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[4.15] W.-K. Yeh, and J.-W. Chou, "Optimum Halo Structure for Sub-0.1mm CMOSFETs," IEEE Trans. Electron Devices., Vol. 48, No. 10, pp.2357-2362, 2001.
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[4.17] Jyh-Haur Wang and B.-K. Liew, "Reduction of a Hot Carrier Effect by an Additional Furnace Anneal Increasing Transient Enhanced Diffusion for Devices Comprised with Low Temperature Spacers," United States Patent, No. 6,117,737, Sep. 12, 2000.

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