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研究生(外文):Meng-Fan Wang
論文名稱(外文):A Study of Novel Gate and Source/Drain Engineering Methods for Metal-Oxide-Semiconductor Transistors
指導教授(外文):Tiao-Yuan HuangHorng-Chih Lin
外文關鍵詞:T-shaped GateTiN Metal GateSub-GateSchottky-BarrierFinGe implant
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我們成功建立一蝕刻複晶矽薄膜程式,適用於不同摻雜種類及濃度的蝕刻,並具有高蝕刻率、均勻性及良好側圖控制(profile control)等。經臨界電壓、崩潰電荷及電荷泵浦(charge pumping)分析佐證可知,此程式對天線元件僅有少量的損傷,可應用於深次微米元件複晶矽閘極製作。
其次,我們成功研製出一新式可同時形成自我對準T型閘極與空氣邊壁子(air spacer)的電晶體結構,簡稱STAIR(self-aligned T-shaped gate and air spacer)。除可有效降低閘極電阻外,空氣邊壁子的形成對降低寄生電容亦深具潛力。然而製程引起的閘極漏電流將損壞氧化層品質。為此,我們引入氮化矽邊壁子大幅降低閘極漏電流,並降低橋接的機率。此結構不僅簡單且與傳統自我對準金屬矽化物(salicide)製程相容,應用於高速元件或高頻電路中將深具潛力。
我們提出一新蕭特基源/汲極SOI場效電晶體結構,係利用一金屬副閘極沈積於氧化層上,偏壓於副閘極上在通道層感應出汲極(field-induced-drain)。依據偏壓模式的不同,同一元件可操作於n或p通道模式且有極佳的開關電流比;對n通道約為107,對p通道可高達108。更重要的一點,電晶體的關閉電流在副閘極適當偏壓下顯得微不足道。此外,在n通道操作時觀察到負微分電導(negative differential conductance, NDC)的現象,成因與大量熱電子在氧化層中被捕捉有關。
其次,沿用具副閘極之蕭特基源/汲極結構製作Fin SOI場效電晶體,完成90 nm通道長度及50 nm Fin寬度的操作,亦可操作於n或p通道模式下且開關電流比高達108。長通道元件中次臨界擺幅隨Fin寬度縮減而下降接近60 mV/dec.的理想值。此外,電晶體的導通電流隨副閘極偏壓的增加而明顯上升,主要受到源極端能障變低所致,但副閘極偏壓增加卻也造成副閘極感應能障下降,而加速臨界電壓下跌;關閉電流在副閘極適當偏壓下亦不明顯。p通道操作時,矽化鉑較矽化鈷有較低的蕭特基能障利於電洞穿遂,因此矽化鉑較矽化鈷有較高的導通電流。
最後,利用低能量與低劑量大角度之鍺離子佈植源/汲極區域,臨界電壓與DIBL(drain-induced barrier lowering)等短通道效應明顯的被抑制,同時有不錯接面漏電流。然而有較差的熱載子免疫力。

In this thesis we have investigated several novel methods for gate and source/drain engineering of MOSFETs. These methods include the design of a universal recipe for etching polysilicon layer with different doping types, the fabrication of a novel T-shaped-gate transistor with air spacer. In addition, we have also studied the thermal stability of metal-gated CMOS transistors. Finally, we have also fabricated novel ambipolar Schottky S/D SOI MOSFETs with field-induced drain, and Schottky FinFETs with field-induced source/drain extensions. In closing, the effects of shallow germanium halo implant on the characteristics of nMOSFETs are also investigated.
To start with, a universal etch recipe which is capable of anisotropically etching polysilicon gate layers of different doping types and concentrations with high etching rate, superior uniformity and good profile control is successfully demonstrated using a commercial TCP etcher. Only minor plasma induced damage is detected as monitored by the antenna devices, indicating that it is feasible for deep sub-micron CMOS process integration.
Next, a novel transistor with self-aligned T-shaped gate and air spacer has been successfully demonstrated, which we dubbed STAIR. The STAIR transistors depict reduced gate resistance, and inherently reduced parasitic capacitance. However, in the original process flow, the gate oxide is exposed during the required long BOE treatment, resulting in large gate leakage. To alleviate this problem, an improved process with the protection of thin nitride layer at the sidewall of poly-Si gate is proposed and proved to effectively reduce the gate leakage as well as bridging probability. The refined process is robust and compatible with salicide processing, which is suitable for future high-speed device and high frequency circuit applications.
To solve the device performance degradation caused by Poly-Si gate depletion effect, the use of metal gate seems to be inevitable. However, metal gate technologies possess many issues. In this thesis, we have investigated the thermal stability of CMOS transistors with TiN metal gate. It is found that oxide thickness and flat-band voltage are both affected by rapid thermal annealing temperature, especially for p-channel devices. Moreover, a hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to occur during high-temperature RTA step as gate length becomes smaller, thus, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel devices.
In this thesis, we have also proposed and fabricated a novel Schottky-barrier source/drain (S/D) silicon-on-insulator (SOI) MOSFET featuring field-induced-drain (FID) structure, which is controlled by a metal field plate (or sub-gate) overlying the passivation oxide. Depending on the bias polarity, ambipolar operation and excellent on/off current ratio is achieved on the unique device. More importantly, the offset leakage current becomes negligible with the proper sub-gate bias. In addition, the negative conduction (NDC) phenomenon is observed in n-channel operation, which is ascribed to the hot electron trapping during device characterization.
Next, we have also applied the FID concept to fabricate a novel Schottky-barrier (SB) FinFET with field induced source/drain extensions. We have successfully demonstrated SB-FinFET with gate length of 90 nm and 50 nm fin width. The new device exhibits superior ambipolar characteristics and high on/off current ratio of 108. In long channel devices, subthreshold slope (SS) approaches the ideal value of 60 mV/dec for narrow-fin-width devices. The output current increases with increasing sub-gate bias, which is presumably due to the tunnel barrier lowering at the source side. The off-state leakage current becomes negligible with the proper sub-gate bias. However, it was found that threshold roll-off is magnified with increasing sub-gate bias, which is probably due to sub gate induced barrier lowering. The silicide material, PtSi with its lower barrier height for holes further enhances the output current, compared with using CoSi2 in p-channel operations.
Finally, we have investigated the use of shallow germanium halo doping on improving the short channel effects of deep-submicron n-channel MOSFETs. We demonstrate that the incorporation of such a shallow Ge halo implant is effective in improving threshold voltage roll-off and drain-induced barrier lowering, while maintaining a low junction leakage. However, hot-carrier degradation dose not seem to be improved by Ge halo implant.

Abstract ( Chinese ) i
Abstract ( English ) iii
Acknowledgment ( Chinese ) vi
Contents vii
Table Captions x
Figure Captions xi
Chapter 1
1.1 General Background 1-1
1.2 Motivation 1-10
1.3 Organization of the Thesis 1-13
References 1-16
Chapter 2
A Universal Recipe for Etching Ploy-Si with Different Doping Types and Concentrations Using a Low Damage TCP Etcher
2.1 Backgrounds and Motivation 2-1
2.2 Experimental 2-3
2.3 Results and Discussion 2-4
2.4 Summary 2-6
References 2-7
Chapter 3
Fabrication and Characterization of Deep-Submicron MOSFETs with Self-Aligned T-Shaped Gate and Air Spacer (STAIR)
3.1 Backgrounds and Motivation 3-1
3.2 Original STAIR transistors 3-3
3.2.1 Experimental 3-3
3.2.2 Device Characterization 3-5
3.3 Improved STAIR Transistors 3-7
3.3.1 Background 3-7
3.3.2 Experimental 3-8
3.3.3 Device Characterization 3-8
3.4 Summary 3-10
References 3-11
Chapter 4
Thermal Stability of PVD TiN Gate and Its Impact on Characteristics of CMOS Transistors
4.1 Backgrounds and Motivation 4-1
4.2 Experimental 4-2
4.3 Results and Discussion 4-3
4.3.1 Junction Characteristics 4-3
4.3.2 Capacitor Characteristics 4-4
4.3.3 Characteristics of CMOS transistors 4-5
4.4 Conclusion 4-11
References 4-12
Chapter 5
Schottky-Barrier SOI MOSFETs with Ambipolar Characteristics
5.1 Backgrounds and Motivation 5-1
5.2 Experimental 5-3
5.3 Results and Discussion 5-4
5.3.1 Ambipolar Characteristics 5-4
5.3.2 Offset Length Effect of FID 5-5
5.3.3 Negative Differential Conduction Phenomenon 5-8
5.4 Summary 5-10
References 5-11
Chapter 6
Schottky-Barrier SOI FINFETs with Excellent Ambipolar Characteristics
6.1 Backgrounds and Motivation 6-1
6.2 Device Structure 6-3
6.3 Device Operation Principle 6-6
6.4 Results and Discussion 6-6
6.4.2 Characteristics of Co-silicided Schottky FinFETs 6-7
6.4.3 Characteristics of Pt-silicided Schottky FinFETs 6-13
6.5 Summary 6-17
References 6-19
Chapter 7
Effects of Shallow Germanium Halo Doping on N-Channel MOSFETs
7.1 Backgrounds and Motivation 7-1
7.2 Experimental 7-2
7.3 Results and Discussion 7-2
7.4 Summary 7-4
References 7-6
Chapter 8
Conclusions and Suggestions for Future Work
8.1 Conclusions 8-1
8.2 Suggestions for Future Work 8-4

[1] K. M. Cham, and S. Y. Chiang, “Device design for the submicron p-channel FET with n+ polysilicon gate,” IEEE Trans. Electron Devices, vol. 31, p.964, 1984.
[2] G. J. Hu and R. H. Bruce, “Design tradeoffs between surface and buried-channel FET’s,” IEEE Trans. Electron Devices, vol. 32, p.584, 1985.
[3] T. N. Ngagen and J. D. Plummer, “A comparison of buried channel and surface channel MOSFET’s for VLSI,” 40th Device Res. Conf., Ft. Collins, Co., paper IIA, June 1982.
[4] S. Y. Chiang, K. M. Cham, and Y. Okazaki, “Optimization of sub-micron p-channel FET structure,” in IEDM Tech. Dig., p.543, 1983.
[5] S. J. Hillenius and W. T. Lynch, “Gate material Work Function Consideration for 0.5 micron CMOS,” in IEDM Tech. Dig., p.147, 1985.
[6] R.A. Chapman et al., ”0.5 micron CMOS for high performance at 3.3V,” in IEDM Tech. Dig., p.19, 1987.
[7] K. Tanaka, and M. Fukuma, “Design methodology for deep submicron CMOS,” in IEDM Tech. Dig., p.628, 1987.
[8] C. Y. Wong, and F. S. Lai, “Ambient and Dopant Effects on Boron Diffusion in Oxides,” App. Phys. Lett., vol. 48, no. 24, p.1658, 1986.
[9] M. Cao, P. V. Voorde, M. Cox, and W. Greene,” Boron diffusion and penetration in ultrathin oxide interface with poly-Si gate,” IEEE Electron Device Lett., vol. 19, p.291, Aug. 1998.
[10] B. Yu, D. H. Ju, N. Kepler, T. J. King, and C. Hu, “Gate engineering for performance and reliability in deep-submicrom CMOS technology,” Symp. VLSI. Technol. Dig. Tech., p.105, 1997.
[11] J. M. Sung, and C. Y. Lu, ”A comprehensive study on p+-polysilicon-gate MOSFETs instability with fluorine incorporation,” IEEE Trans. Electron Devices, vol.37, no.11, p.2312, 1990.
[12] Okazaki, T. Kobayashi, H. Inokawa, S. Nakayama, M. Miyake, T. Morimoto and Y. Yamamoto,” Sub-1/4-mm dual-gate CMOS technology using in-situ doped polysilicon for nMOS and pMOS gates,” IEEE Trans. Electron Devices, vol. 42, p.1583, 1995.
[13] Y. Okazaki et al., “Sub-1/4-mm dual gate CMOS technology using in situ doped polysilicon for n and pMOS gates,” symp. VLSI Technol. Dig., p.95. 1995.
[14] B. Davari, W. H. Chang, K. E. Petrilio, C. Y. Wong, D. Moy, Y. Taur, M. R. Wordeman, J. Y.-C. Sun, C. C.-H, Hsu, and M. R. Polcari, “A high performance 0.25-mm CMOS technology: II-technology,” IEEE Trans Electron Devices, vol. 39, p.967, 1992.
[15] K. Fuji, K. Kikuta, and K. Kikkawa, “Sub-quarter-micron Ti salicide technology with in situ silicidation using high-temperature sputtering,” in VLSI Tech. Dig., p.57, 1995.
[16] S. P. Murarka, D. B. Fraster, A .K. Sinha, H. J. Levinstein, E. J. Lloyd, R. Liu, D. S. Williams, and S. J. Hillenius, “Self-aligned cobalt disilicide for gate and interconnection and contacts to shallow junctions,” J. Appl. Phys., vol. 58, no. 2, p.971, 1985.
[17] K. Inoue, K. Mikagi, H. Abiko, and T. Kikkawa, “A new cobalt salicide technology for 0.15-mm CMOS using high-temperature sputtering and in-situ vacuum annealing,” in IEDM Tech. Dig., p.445, 1995.
[18] T. Ohguro, S. Nakamura, E. Morifuji, T. Yoshitomi, T. Morimoto, H. Harakawa, H. S. Momose, Y. Katsumata, and H. Iwai, ”0.25-mm CoSi2 salicide CMOS technology thermally stable up to 1000℃ with high TDDB reliability,” in VLSI Tech. Dig., p.101, 1997.
[19] J. A. Kittl, Q. Z. Hong, C. P. Chao, I. C. Chen, S. O’Brien, and M. Hanratty,” Salicide for 0.1mm gate lengths: A comparative study of one-step RTP Ti with Mo doping, Ti with pre-amorphization, and Co processes, “in VLSI Tech. Dig., p.103, 1997.
[20] G. L. Miles, R. W. Mann, and J. E. Bertsch, “TiSi2 phase transformation characteristics on narrow devices,” Thin Solid Films, p.469, 1996.
[21] J. A. Kittl, M. A. Gribelyuk, and S. B. Samavedam, “Meahanism of low temperature C54 TiSi2 formation bypassing C49 TiSi VTH: Effect of microctructure and Mo impurities on the Ti-Si reaction path,” Appl. Phys. Lett. vol. 73, no. 7, p.900, 1998.
[22] D. Hisamoto, K. Umeda, Y. Nakamura and S. Kimura, “ A low-resistance self-aligned T-shaped gate for high-performance sub-0.1-mm CMOS,” IEEE Trans. Electron Devices, vol. 44, p.951, 1997.
[23] C. P. Chao, K. E. Violette, S. Unnikrishnan, M. Nandakumar, R. L. Wise, J. A. Kittl, Q. Z. Hong and I. C. Chen,” Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13 mm CMOS technologies,” in IEDM Tech. Dig., p.103, 1997.
[24] A. Chatterjee et al., ”Sub-100nm gate length metal gate NMOS transistors fabricated by a replacement gate process,” in IEDM Tech. Dig., p.821, 1997.
[25] H. Wakabayashi, T. Yamamoto, T. Tatsumi, K. Tokunaga, T. Tamura, T. Mogami and T. Kunio,” A high-performance 0.1-mm CMOS with elevated salicide using novel Si-SEG process,” in IEDM Tech. Dig., p.99, 1997.
[26]T. Ohguro et al., “High performance RF characteristics of raised gate/source/drain CMOS with Co salicide,” Symp. VLSI. Technol. Dig. Tech., p.136, 1998.
[27] H. C. Lin, R. Lin, W. F. Wu, R. P. Yang, M. S. Tsai, T. S. Chao and T. Y. Huang, “A novel self-aligned T-shaped gate process for deep submicron Si MOSFET’s fabrication,” IEEE Electron Device Lett., vol. 19, p.26 1998.
[28] T. Ushiki, K. Kawai, I. Ohshima and T. Ohmi, “Chemical reaction concerns of gate metal with gate dielectric in Ta gate MOS devices: an effect of self-sealing barrier configuration interposed between Ta and SiO2,” IEEE Trans. Electron Devices, vol.47 p.2201, 2000.
[29] D. H. Lee et al., “Characteristics of CMOSFET’s with sputter-deposited W/TiN stack gate,” in Symp. VLSI Tech. Dig., p.119, 1995.
[30] H. Noda et al., “Tungsten gate technology for quarter-micron application,” in Ext. Abst. 1995 Int. Conf. Solid State Device and Materials, p.225, 1995.
[31] H. Shimada, Y. Hirano, T. Ushiki, and T.Ohmi, “Threshold voltage adjustment in SOI MOSFET’s by employing tantalum for gate material,” in IDEM Tech. Dig., p.881, 1995.
[32] D. H. Lee, K. H. Yeom, M. H. Cho, N. S. Kang, and T. S. Shim,“ Gate oxide integrity (GOI) of transistors with W/TiN stacked gate,” in Symp. VLSI Tech. Dig., p.208, 1996.
[33] T. Ushiki, M.-C. Yu, Y. Hirano, H. Shimada, M. Morita, and T. Ohmi,” Reliable tantalum gate fully-depleted-SOI MOSFET’s with 0.15 mm gate length by low-temperature processing below 500℃,” in IEDM Tech. Dig., p.117, 1996.
[34] Y. Momiyama, H. Minakata, and T. Sugii, “Ultra-thin Ta2O5/SiO2 gate insulator with TiN gate technology for 0.1 mm MOSFET’s ,” in Symp. VLSI Tech. Dig., p.135, 1996.
[35] H. Yang et al., “A comparison of TiN processes for CVD W/TiN gate electrode on 3 mm gate oxide,” in IEDM Tech. Dig., p.459, 1997.
[36] J. C. Hu et al., “Feasibility of using W/TiN as metal gate for conventional 0.13 mm CMOS technology and beyond,” in IEDM Tech Dig., p.825, 1997.
[37] B. Maiti et al., “PVD TiN metal gate MOSFET’s on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrate for deep sub-quarter micron CMOS technology,” in IEDM Tech. Dig., p.781, 1998.
[38] A. Chatterjee et al., “CMOS metal replacement gate transistor using tantalum pentoxide gate oxide,” in IEDM Tech. Dig., p.777, 1998.
[39] A. Yagishita et al., “High performance metal gate MOSFET’s fabricated by CMP for 0.1 mm regime.” in IEDM Tech. Dig., p.785, 1998.
[40] K. Nakajima, Y. Akasaka, M. Kaneko, M. T.amaoki, Y. Yamada,” Work function controlled metal gate electrode on ultrathin gate insulators,” in Symp. VLSI Tech. Dig., p.95, 1999.
[41] J. Chen et al., “0.18mm metal gate fully-depleted SOI MOSFETs for advanced CMOS applications,” in Symp. VLSI Tech., P.25, 1999.
[42] E. Josse, and T. Skotnicki, “Polysilicon gate with depletion-or-metallic gate with buried channel:what evil worse?,” in IEDM Tech. Dig., p.661, 1999.
[43] Q. Lu et al., “Dual-metal gate technology for deep-submicron CMOS transistors,” in Symp. VLSI Tech., P.72, 2000.
[44] M. P. Lepselter, and S. M. Sze, “SB-IGFET: An Insulated-Gate Field-Effect Transistor Using Schottky Barrier Contacts as Source and Drain,” Proc. IEEE, 56, p.1088, 1968.
[45] C. Wang, J. P. Synder, and J. R. Tucker,” Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 74, p.1174, 1999.
[46] J. R. Tucker,” Schottky barrier MOSFETs for silicon nanoelectronics,” WOFE’97 Proceedings., Frontiers in electronics, p.97, 1997.
[47] Q. Z. Zhao, F. Klinkhammer, M. Dolle, L. Kappius, S. Mantl,” A novel silicide nanopatterning nethod for the fabrication of ultra-short channel Schottky-tunneling MOSFET’s,” Microelec. Engineering, vol.50, p.133, 2000.
[48] C. K. Huang, W. E. Zhang, and C. H. Yang,” Two-dimensional numerical simulation of Schottky barrier MOSFET with channel length to 10 nm,” IEEE Trans. Electron Devices, vol.45 p.842, 1998.
[49] B. Winstead and U. Ravaioli,” Simulation of Schottky barrier MOSFET’s with a coupled quantum injection/Monte Carlo Technique,” IEEE Trans. Electron Devices, vol.47, p.1241, 2000.
[50] W. Saitoh, A. Itoh, S. Yamagami and M. Asada,” Analysis of short-channel Schottky source/drain metal-oxide-semiconductor field-effect-transistor on Silicon-on-insulator substrate and demonstration of sub-50-nm n-type devices with metal gate,” Jpn. J. Appl. Phys., vol. 38, p.6226, 1999.
[51] J. Kedzierski, P. Xuan, E. H. Anderson, J. Boker, T. J. King, and C. Hu,” Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime,” in IEDM Tech. Dig., p.57, 2000.
[52] J. P. Snyder, C. R. Helms, and Y. Nishi,” Experimental investigation of a PtSi source and drain field emission transistor,” Appl. Phys. Lett., vol. 67, p.1420, 1995.
[53] L. E. Calvet, H. Luebben, M .A. Reed, C. Wang, J. P. Snyder, and J. R. Tucker,” Suppersion of leakage current in Schottky barrier metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 91, p.757, 2002.
[54] M. Nishisaka, and T. Asano,“ Reduction of the floating body effect in SOI MOSFETs by using Schottky source/drain contacts,” Jpn. J. Appl. Phys., Vol. 37, p.1295, 1998.
[55] M. Sugino, L. A. Akers, and M .E. Rebeschini,” Latchup-free Schottky-barrier CMOS,” IEEE trans. Electron Devices, vol. 30, p.110, 1984.
[56] T. Y. Huang, I. W. Wu, A. G. Lewis, A. Chiang, and R. H. Bruce, “A simpler 100-V polysilicon TFT with improved turn-on characteristics,” IEEE Electron Device Lett.,, vol. 11, p.244, 1990.
[57] H. C. Lin, C. Y. Lin, K. L. Yeh, R. G. Huang, M. F. Wang, C. M. Yu, T. Y. Huang, and S. M. Sze,” A novel implantless MOS thin-film transistor with simple processing, excellent performance and ambipolar operation capability,” in IEDM Tech. Dig., p.857, 2000.
[58] K. L. Yeh, H. C. Lin, R. G. Huang, R. W. Tsai, and T. Y. Huang,” Conduction for off-state leakage current of Schottky barrier thin-film transistors,” Appl. Phys. Lett., vol. 79, p.635, 2001.
[59] H. C. Lin, K. L. Yeh, T. Y. Huang, R. G. Huang, and S. M. Sze,” Ambipolar Schottky-Barrier TFTs,” IEEE Trans. Electron Devices, vol. 49, p.264, 2002.
[60] H. S. Wong, D. J. Frank, Y. Taur, and J. M. C. Stork, “Design and Performance considerations for sub-0.1mm double-gate SOI MOSFET’s,” in IEDM Tech. Dig., 1994, p.747, 1994.
[61] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Boker, and C. Hu, “ FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, p.2320, 2000.
[62] X. Huang et al.,” Sub-50 nm p-channel FinFET,” IEEE Trans. Electron Devices, vol. 48, p.880, 2001.
[63] N. Linder, L. Chang, Y. K. Choi, E. H. Anderson, W. C. Lee, T. J. King, J. Boker, and C. Hu, “ Sub-60-nm quasi-planar FinFETs fabricated using a simplified process,” IEEE Electron Device Lett.,, vol. 22, p.487, 2001.
[64] Y. K. Choi, T. J. King, and C. Hu,“ A spacer patterning Technology for Nanoscale CMOS,” IEEE Trans. Electron Devices., vol. 49, p.436, 2002.
[65] H. —S. P. Wong, D. J. Franket, and P. M. Solomon, “Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation,” in IEDM Tech. Dig., p.407, 1998.
[66] D. Hisamoto, W. C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T. J. King, J. Bokor, and C. Hu, “A folded-channel MOSFET foe deep-sub-tenth micron era,” in IEDM Tech. Dig., 1998 pp.1032-1034.
[67] J. R. Pfiester, M. E. Law, and R. W. Dutton, “Improved MOSFET Short-Channel Device Using Germanium Implantation,” IEEE electron Device Lett., vol. 9, p-.343, 1988.
[68] M. C. Ozturk, J. J. Wortman, C. M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W. K. Chu and C. Lee, “Optimization of the Germanium Preamorphization Conditions for Shallow-Junction Formation,” IEEE Trans. Electron Dev., vol. 35, p.659, 1988.
[69] J. R. Pfiester and J. R. Alvis, “Improved CMOS Field Isolation Using Germanium/Boron Implantation,” IEEE Electron Device Lett., vol. 9, p.391, 1988.
[70] D. S. Wen, S. H. Goodwin-Johansson, “Tunneling Leakage in Ge-Preamorphized Shallow Junctions,” IEEE Trans. Electron Dev., vol. 35, p.1107, 1988.
[71] C. Mazure and M. Orlowski, “Guidelines for Reverse Short-Channel Behavior,” IEEE electron Device Lett., vol. 10, p.556, 1989.
[72] H. I. Hanafi, W. P. Nobel, R. S. Bass, K. Varahramyan, Y. Lii and A. J. Dally, “A Model for anomalous Short-Channel Behavior in submicron MOSFET’s,” IEEE electron Device Lett., vol. 14, p.575, 1993.
[73] H. Jacobs, A. V. Schwerrin, D. Scharfetter and F. Lau, “MOSFET Reverse Short Channel Effect Due to Silicon Intersitial Capture in Gate Oxide,” in IEDM Tech. Dig., p.307, 1993.
[74] C. Y. Chang, C. Y. Lin, J. W. chou, C. H. Hsu, H. T. Pan, and J. Ko, “Anomalous Reverse short-Channel Effect in p+ polysilicon Gated P-channel MOSFET,” IEEE electron Device Lett., vol. 15, p.437, 1994.
[75] P. M. Rousseau, S. W. Crowder, P. B. Griffin, and L. D. Plummer, “Arsenic Deactivation Enhanced Diffusion and Reverse Short-Channel Effect,” IEEE electron Device Lett., vol. 18, p.42, 1997.
[76] A. Sadovnikov, A. Kalnitsky, A. Bergement, and P. Hopper, “The effects of Polysilicon Doping on the reverse Short-Channel Effect in Sub-Quarter Micron NMOS Transistors,” IEEE Trans. Electron Dev., vol. 48, p.393, 2001.
[77] C. S. Rafferty, H. H. Vuong, S. A. Eshraghi, M. D. Giles, M. R. Pinto, S. J. Hillenius, “Explanation of Reverse Short channel Effect by Defect Gradients,” in IEDM Tech. Dig., p.311, 1993.
[78] T. Hori, ”1/4-mm LATID (large-tilt angle implanted Drain) Technology for 3.3-V Operation,” in IEDM Tech. Dig., p.777, 1989.

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