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研究生:林孟學
研究生(外文):Meng-Hsueh, Lin
論文名稱:高效能管線化之直接數位頻率合成器設計
論文名稱(外文):An Efficient Pipeline Direct Digital Frequency Synthesizer Based on a Novel Interpolation Algorithm
指導教授:陳紹基陳紹基引用關係
指導教授(外文):Sau-Gee, Chen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
中文關鍵詞:直接數位頻率合成器
外文關鍵詞:DDFSNCO
相關次數:
  • 被引用被引用:3
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  • 下載下載:42
  • 收藏至我的研究室書目清單書目收藏:1
本篇論文提出一新式的直接數位頻率合成器,具有高速、低複雜度和高頻譜純度的特性。新式的直接數位頻率合成器是根據一新穎的內插演算法來達成正(餘)弦函數的計算,此新演算法精確地描述內插所造成的誤差。新式的直接數位頻率合成器藉著管線化的架構,不斷地執行內插以產生所要求得的數值,整個電路只需N個加法和一個大小為 字串的表即可,其中N為輸出值的位元長度。所需記憶體量與計算硬體面積比現有最佳同類型之數位頻率合成器少。模擬結果顯示當N=16時,SFDR可達到100dBc,而表的大小也只有304個位元。此外由於管線化架構的關係,新式的直接數位頻率合成器有很高的資料產生率和相當短、約一個加法延遲的時脈週期。

In this thesis, we propose a new direct digital frequency synthesizer (DDFS). It has the merits of high speed, low complexity and high spectrum purity. It is based on a novel interpolation algorithm for sinusoidal functions. The algorithm accurately characterizes the interpolation error. With a small lookup table of words, the DDFS successively interpolate the target value in a pipeline fashion using only N addition operations, where N is the output word length. Simulation shows that for N=16-bit example, 100dBc of SFDR (spurious free dynamic range) is achieved, with a lookup table of only 304 bits. In addition, due to its pipeline structure, the new DDFS have a very high throughput rate and a very short cycle time of about an adder delay. The new design has a smaller table size and less datapath requirement than the best known DDFS by Madisetti et al, at the same speed performance.

Chapter 1 Introduction ………………………………………… 1
1.1 Background ………………………………………1
1.2 Organization of the Thesis …………………3
Chapter 2 Applications of Direct Digital Frequency Synthesizer .... 5
2.1 Modulation by DDFS …………………………… 5
2.1.1 Amplitude Modulation ………………………6
2.1.2 Phase Modulation ……………………………8
2.1.3 Frequency Modulation ………………………9
2.1.4 Single Sideband Modulation ………………10
2.1.5 Amplitude Shift Keying ……………………12
2.1.6 Phase Shift Keying …………………………13
2.1.7 Quadrature Amplitude Modulation ………15
2.1.8 Frequency Shift Keying ……………………16
2.1.9 Frequency Division Multiplexing ………18
2.1.10 Frequency Hopping …………………………19
2.2 Integrating DDFS with PLL or Mixer ………20
2.2.1 Integrating DDFS with PLL ………………21
2.2.2 Integrating DDFS with Mixer ……………21
Chapter 3 An Overview of Frequency Synthesizer and Classification of Existing DDFS …………...………24
3.1 Frequency Synthesizer …………………………24
3.1.1 Direct Analog Synthesizer …………………24
3.1.2 Phase Locked Loop ……………………………25
3.1.3 Direct Digital Frequency Synthesizer …26
3.1.4 Comparison between Three Popular Techniques ..28
3.1.5 Frequency Synthesizer Parameters …………29
3.2 The Existing DDFS Algorithms …………………30
3.2.1 ROM-based and ROM Compression Techniques …31
3.2.2 The Initial Guess Algorithm …………………32
3.2.3 IIR Filter Based DDFS Design ………………34
3.2.4 Nonlinear DAC-based DDFS ……………………37
3.2.5 CORDIC Algorithm Based DDFS…………………38
Chapter 4 The New Interpolation Algorithm and Architecture for DDFS …………………………………………………….41
4.1 The New Interpolation Algorithm ………………41
4.1.1 The 0th-order Interpolation Algorithm ……42
4.1.2 The 2nd-order Interpolation Algorithm ……43
4.1.3 The 4th-order Interpolation Algorithm ……44
4.1.4 Demonstration of the 2nd-order Algorithm …45
4.2 The New Interpolation Architecture …………46
4.2.1 Phase Accumulator ………………………………47
4.2.2 Control Block ……………………………………49
4.2.3 Radian Converter ………………………………51
4.2.4 Sine/Cosine Generator …………………………53
4.2.5 Mapping Block ……………………………………57
4.3 The Modified DDFS Architecture ………………59
4.3.1 The First Modified DDFS ………………………60
4.3.2 The Second Modified DDFS ……………………62
4.4 Performance Comparison …………………………63
Chapter 5 Software/Hardware Co-Simulation, Verification and Performance Comparison …………………………67
5.1 C Language, Verilog and Matlab Simulation Results …………………67
5.1.1 C Language Simulation ………………………67
5.1.2 Verilog Simulation …………………………68
5.1.3 Synthesis Results ……………………………72
5.1.4 SFDR Simulations by Matlab with Verilog Outputs …………………76
5.1.5 The Modified DDFS Simulation Results ……83
5.2 FPGA Implementation Results …………………86
Chapter 6 Conclusion …………………………………91
Bibliography …………………………………………………… 93
Appendix ……………………………………………………… 96
Autobiography …………………………………………………120

[1] Technical Staff, Osicm Technologies Inc., “Direct-Digital Frequency Synthesis, A Basic Tutorial,”.
[2] M.H. Lin et al, “An Efficient Pipeline Direct Digital Frequency Synthesizer Based on a Novel Interpolation Algorithm,” in Proc. 15th ECCTD, pp. 273-276, 2001.
[3] S. Haykin, ”Communication System,” 4th ed., John Wiley & Sons, Inc., pp. 19, 2001.
[4] L.K. Tan, and H. Samueli, “A 200-MHz Quadrature Digital Synthesizer/Mixer in 0.8-μM CMOS,” IEEE Custom Integrated Circuits Conference, pp. 4.41-4.44, 1994.
[5] E. Best Roland, “Phase-Locked Loops: Theory, Design, and Applications,” McGraw-Hill, 1984.
[6] B.G. Goldberg, Sciteq Electronics, “Digital Techniques in Frequency Synthesis,” McGraw-Hill, pp. 4, 1996.
[7] J. Tierney, C.M. Rader, and B. Gold, “A Digital Frequency Synthesizer,” IEEE Trans. Audio and Electro-acoustics, vol. AU-19, no. 1, pp. 48-57, Mar. 1971.
[8] D.A. Sunderland, R.A. Strauch, S.S. Wharfield, H.T. Peterson, and C.R. Cole, “CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum Communications” IEEE Journal of Solid State Circuits, vol. SC-19, pp. 497-505, Aug 1984.
[9] S. Liao and L.G. Chen, “A Low-Power Low-Voltage Direct Digital Frequency Synthesizer,” in Proc. 1997 Int. Symp. VLSI Technology, Sytems, Applications, pp. 265-269, June 1997.
[10] J.C. chih, J.Y. Chou and S.G. Chen, “An Efficient Direct Digital Frequency Synthesizer Based on Two-Level Table Lookup,” in Proc. 2001 IEEE International Frequency Control Symp., pp. 824-827, 2001.
[11] R. Uusikartano, and J. Niitylahti, “A Periodical Frequency Synthesizer for A 2.4-GHz Fast Frequency Hopping Transceiver,” IEEE Transaction on Circuits and Systems-Ⅱ: Analog and Digital signal processing, vol.48, pp. 912-918, Oct. 2001.
[12] H. T. Nicholas III et al., “The Optimization of Direct Digital Frequency Synthesizer Performance in the Presence of Finite Word Length Effects,” in Proc. 42nd Annu. Frequency Control Symp., pp. 357—363, 1988.
[13] A. Yamagishi et al., “A 2-V, 2-GHz Low-Power Direct Digital Frequency Synthesizer Chip-Set for Wireless Communication,” IEEE J. Solid-State Circuits, vol. 33, pp. 210-217, Feb. 1998.
[14] A.M. Sodagar, and G.R. Lahihi, “Mapping From Phase to Sine-Amplitude in Direct Digital Frequency Synthesizers Using Parabolic Approximation,” IEEE Transactions on Circuits and System, vol. 47, pp. 1452-1457, Dec. 2000.
[15] A.M. Sodagar, and G.R. Lahihi, “Second-Order Parabolic Approximation: A New Mathematical Approximation Dedicated to ROM-less DDFSs,” The 12th International Conference on Microelectronics, Tehran, Oct.31-Nov.2, 2000.
[16] K.I. Palomaki, and J. Niittylahti, “Direct Digital Frequency Synthesizer Architecture Based on Chebyshev Approximation,” Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on, vol.2, pp. 1639-1643, 2000.
[17] M.M. Al-Ibrahim, “A Simple Recursive Digital Sinusoidal Oscillator with Uniform Frequency Spacing,” Proceeding of The 2001 IEEE International Symposium on Circuits and Systems, vol.2, pp. 689-692, 2001.
[18] N.J. Fliege, and J. Wintermantel, “Complex Digital Oscillators and FSK Modulators,” IEEE Transactions on Signal Processing, vol. SP-40, pp. 333-342, Feb. 1992.
[19] A.I. Abu-Haija and M.M. Al-Ibrahim, “Improving Performance of Digital Sinusoidal Oscillators by Means of Error Feedback Circuits,” IEEE Transactions on Circuits and Systems, vol. CAS-33, pp. 373-380, Feb. 1986.
[20] S. Mortezapour and E.K.F. Lee, “Design of Low-Power ROM-less Direct Digital Frequency Synthesizer Using Nonlinear Digital-to-Analog Converter,” IEEE Journal of Solid-State, vol.34, pp. 1350-1359, Oct. 1999.
[21] A. Madisetti et al, “A 100-MHz, 16-bit, Direct Digital Frequency Synthesizer with A 100-dBc Spurious-Free Dynamic Range,” IEEE J. Solid-State Circuits, vol. 34, pp. 1034-1043, Aug. 1999.
[22] J. Volder, “The CORDIC Trigonometric Computing Technique,” IEEE Trans. Computers, vol. EC-8, pp. 330—334, Sept. 1959.
[23] H. T. Nicholas and H. Samueli, “A 150 MHz Direct Digital Frequency Synthesizer in 1.25-μm CMOS with —90dBc Spurious Performance,” IEEE J. Solid-State Circuits, vol. 26, pp. 1959-1969, Dec. 1991.

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