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研究生:江蕙如
研究生(外文):Hui-Ru Jiang
論文名稱:深次微米技術連線最佳化之研究
論文名稱(外文):Interconnect Optimization for Deep Submicron Technology
指導教授:周景揚周景揚引用關係張耀文張耀文引用關係
指導教授(外文):Prof. Jing-Yang JouProf. Yao-Wen Chang
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:116
中文關鍵詞:深次微米技術連線最佳化
外文關鍵詞:Interconnect OptimizationDeep Submicron Technology
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半導體工業協會在一九九九年撰寫的製程技術演進表揭露了進入奈米(Nanometer)時代之後,單顆晶片將可容納超過二億個電晶體。面臨如此龐大又複雜的電路,維持時序一致性(Timing closure)與掌握設計收斂度(Design convergence)將會是最大的難題。另一方面,自深次微米時代以降,電路之連線(Interconnect)是決定效能(Performance)最關鍵的因素。但是,傳統的實體設計(Physical design)流程中,必須到繞線(Routing)甚至是佈局(Layout)完成後才處理連線最佳化的問題。當模組(Module)之間的訊號溝通的量急遽上升,這樣的處理方式將無法應付,尤其是到了設計流程的後期,大部分下層的面積以及上層的繞線區域都已被佔用,更使得問題困難重重。
為了解決這樣的問題,本篇論文提出了以連線為導向之設計流程(Interconnect-driven design flow)。此流程結合了安插緩衝器(Buffer insertion),安排導線順序(Wire ordering),調整邏輯閘與導線大小(Gate and wire sizing)三種方法。為了在早期估計連線部分的延遲與整體的面積,我們提出了將緩衝區的規劃(Buffer block planning)整合到平面規劃(Floorplanning)的方法。另外在後置佈局最佳化(Post-layout optimization)階段,我們透過重新安排導線順序的方式將訊號變動對雜訊干擾(Crosstalk)的影響減至最小,之後藉由調整邏輯閘與導線大小的技巧同時對雜訊干擾,訊號延遲,整體面積,功率消耗,甚至是製程變異(Process variation)對雜訊干擾的影響,作最佳化。本篇論文中所探討的幾何規劃(Geometric program)問題都是利用拉氏鬆綁法(Lagrangian relaxation)求得最佳解,實驗結果顯示拉氏鬆綁法非常適合應用在實體設計最佳化的問題。
As revealed by the 1999 international technology roadmap for semiconductors, technology will soon shrink into below 0.1 micrometer and the chip complexity will be over 200 million transistors. For such large and complex design, timing closure and design convergence are the most important concerns. Further, for deep submicron designs, interconnect dominates circuit performance. However, the conventional physical design flow handles interconnect optimization at the routing or the post-layout stage. When the amount of communication among modules rapidly increases, it is almost impossible to remedy interconnect only at late stages, since most silicon and routing resources are occupied.
To overcome the problem, in this dissertation, we propose an interconnect-driven design flow, incorporating buffer insertion, wire ordering, and gate and wire sizing into the design flow. To deal with interconnect delay and overall area, we integrate buffer block planning into floorplanning. At post-layout optimization, we first apply wire ordering to minimize the impact of switching behavior on crosstalk. Using gate and wire sizing, we then simultaneously optimize crosstalk, delay, area, power, and even the impact of process variation on crosstalk. Further, we optimally solve the geometric programs formulated in this dissertation by Lagrangian relaxation. It can be seen that Lagrangian relaxation is suitable for physical design problems.
Chapter 1. Introduction
Chapter 2. Simultaneous Floorplanning and Buffer Block Planning
Chapter 3. Crosstalk-Driven Interconnect Optimization
Chapter 4. Reliable Crosstalk-Driven Interconnect Optimization
Chapter 5. Conclusion
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