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研究生:陳奇祥
研究生(外文):Darren Chi-Hsiang Chen
論文名稱:低溫複晶矽薄膜電晶體的新結構開發與關鍵製程技術
論文名稱(外文):New Structure Development and Key Process Technologies for Low Temperature Processed Poly-Si Thin-Film Transistors
指導教授:葉清發
指導教授(外文):Ching-Fa Yeh
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:187
中文關鍵詞:低溫複晶矽薄膜電晶體笑氣電漿處理液相沈積氧化膜雙緩衝汲極複晶矽薄膜電晶體氘氣電漿處理金屬引發橫向再結晶
外文關鍵詞:LTP poly-Si TFT'sN2O-plasma treatmentLiquid-phase deposited oxideDual-buffer-drain poly-Si TFT'sDeuterationMetal-induced laterally crystallization
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利用複晶矽薄膜電晶體製作畫素元件及週邊驅動電路並將之積體化於大面積玻璃基座已是未來製作平面液晶顯示器的趨勢,而複晶矽薄膜電晶體的低溫製程技術將會是一個重要的關鍵。在本論文中,我們開發了兩種新結構,並且利用了幾種低溫製程技術來改善複晶矽薄膜電晶體的元件特性,包括閘極絕緣層沈積後之退火(post-annealing)技術,通道缺陷的填補技術以及金屬再結晶法(MILC)主動層技術。
在第一個部份中,我們首先開發了一種新結構叫雙緩衝汲極(DBD-TFT)來改善元件的開關電流比,它不僅能降低漏電流,並且也維持了開電流。它主要是結合了雙閘極(Double Gate)與場引發汲極(Field-Induced Drain)等結構的優點,進而改善了汲極附近的電場與介面特徵。DBF-TFT能穩定的控制漏電流,同時也適合高壓(80V)的操作。此外,我們也開發了另一種新結構叫自引發式汲極(Self-Induced Lightly-Doped Drain),它主要是利用氫化時造成LPD-SiO2覆蓋層(LPD-SiO2 ILD)的帶電效應,進而感應汲極附近輕微的導電粒子,進而使的元件開關特性上獲得改善。
在第二個部分中,對於液相沈積二氧化矽閘極絕緣層沈積後之退火技術而言,我們提出了利用低溫(~300oC)笑氣(N2O)電漿退火來取代傳統的600oC氧氣爐管退火處理。由物/化性及電性的研究上顯示經由笑氣電漿退火處理過的液相沈積二氧化矽膜有較高的崩潰電場及較低的界面缺陷密度(Interface State Density)。此外,笑氣電漿退火可以改善液相沈積二氧化矽膜富含矽(Si-Rich)的現象。這種閘極退火技術已成功地應用到以液相沈積二氧化矽膜作為閘極絕緣層的複晶矽薄膜電晶體上,而且擁有相當優異的元件電特性及可靠性。笑氣電漿退火不僅可以改善閘極二氧化矽膜的品質,同時也可以有效地填補複晶矽通道的缺陷。
在第三個部分中,我們利用氘氣(Deuterium)電漿處理取代傳統的氫氣電漿處理,作為低溫製作複晶矽薄膜電晶體的缺陷填補技術。氘氣電漿處理可以改善薄膜電晶體的電特性,尤其對載子移動率及元件可靠性方面,這可以歸功於矽和氘氣鍵結間巨大的同位素效應(Isotope Effect)及強的耦合效能(Coupling Efficiencies)。另外,在氘氣電漿處理之後,我們也試著再加上笑氣電漿處理來填補低溫製作複晶矽薄膜電晶體的缺陷。我們發現經由氘氣電漿處理後再加上笑氣電漿處理比單獨用氘氣電漿處理或笑氣電漿處理更能有效地抑制熱載子加壓退化(Hot-Carrier Degradation)。
在最後一個部份中,低溫(550oC)鎳金屬引發橫向再結晶技術(MILC)成功的應用在低溫複晶矽薄膜電晶體,其中並探討了不同主動層材料(SiH4 and Si2H6)的再結晶元件特性。我們也提出了一個新穎的技術,也就是利用雙閘極結構(U-Shape)來防止側向結晶的結合邊界形成在元件通道中。這個技術大幅降低汲極附近橫向電場而有效抑制了元件的漏電流。在可靠性上,我們發現到氘化的MILC-TFT比起氫化有較佳的熱載子抑制效果。最後,我們提出一個類摻雜缺陷密度(Donor-Like Trap States)的模式來解釋MILC-TFT經過熱載子加壓後,在漏電流方面反而變好的現象。

Utilizing polycrystalline silicon thin-film transistors (poly-Si TFT’s) as on-glass pixel switching elements and peripheral driver circuits is the future trend for fabricating active-matrix liquid-crystal displays (AMLCDs). Low-temperature processes (LTP) for poly-Si TFT’s are important issues. In this thesis, we utilized several low-temperature technologies to improve poly-Si TFT’s' performance, including new structure development, gate-oxide post-annealing, channel defect passivation and metal induced recrystallization of α-Si.
First of all, ON/OFF current ratio of Poly-Si TFT’s has been improved by using a novel structure called the dual-buffer drain (DBD). The new DBD TFT not only reduces the anomalous off-current, but also maintains a high on-current. It mainly combines features of the double-gate and the field-induced drain structures, so that owns advantages of low electric field near the drain junction and good drain junction characteristics. Furthermore, it will be shown that the DBD TFT is superior in off-current stability to the FID TFT. Finally, we will discuss high voltage operation for the DBD TFT.
The technology of growing liquid-phase deposited (LPD) silicon dioxide has been successfully used in fields of gate insulator and insulating capping layer. Here, a novel idea of charged LPD oxide by hydrogen plasma treatment is also proposed and applied in a new TFT structure as its interlayer. The new structure is named as self-induced lightly-doped-drain (SI-LDD) poly-Si TFT’s. The new structure, utilizing charged LPD interlayer, not only effectively reduces OFF-current but also still feeds enough large ON-current. In the reliability, The SI-LDD poly-Si TFT’s reveals an acceptable instability under large bias stress.
On the other hand, low temperature (~300oC) N2O-plasma post-treatment for liquid-phase deposited (LPD) gate oxide has been proposed for the first time. It successfully takes the place of conventional furnace annealing in O2 ambient. Results of physicochemical and electrical characteristics show that N2O-plasma post-treated LPD-SiO2 has high electrical breakdown field and low interface state density. In addition, N2O-plasma treatment also improves the Si-rich phenomenon of LPD-SiO2. From the comparison with pure N2O-plasma oxidation film, LPD-SiO2 with the short time re-oxidation in N2O plasma plays an important role in relieving interfacial stress. Finally, the novel technology is applied to the gate oxide of low temperature processed (LTP) poly-Si TFT’s. The device performance reveals excellent electrical characteristics, and the reliability shows a satisfactory result, as well as the gate oxide reliability. It is believed that the N2O-plasma post-treatment not only improves the oxide quality, but also effectively passivates the trap states of poly-Si TFT’s.
Futhermore, for defect passivation technology of LTP poly-Si TFT’s, we utilize deuterium (D2) plasma to replace the conventional hydrogen (H2) plasma treatment. D2-plasma passivation can improve enormously the TFT’s' performance, particularly in carrier mobility and reliability. This improvement can be attributed to the giant isotope effect and strong coupling efficiencies by the Si-D bonds. In addition, the effects of D2-plasma followed by N2O-plasma passivation (D2-N2O-plasma) on LTP poly-Si TFT’s were also investigated. It was found that D2-N2O-plasma passivation is more effective in improving the hot-carrier immunity of poly-Si TFT’s than D2-plasma or N2O-plasma passivation only.
Finally, Low-temperature (<550oC) Ni-metal induced lateral crystallization (MILC) has been applied to high performance poly-Si TFT’s process. The MILC-TFT with Si2H6 deposited-Si layer performs better performance than that with SiH4 deposited -Si layer due to its easier re-crystallized properties. Moreover, a smart “U-shape” double-gate structure for MILC-TFT’s is proposed to improve the problem of metal-silicide residues and reduce OFF-current. The OFF-current is reduced significantly two orders of magnitude and the threshold voltage is improved 35%. For hot-carrier reliability, MILC-TFT’s show much smaller degradation than SPC-TFT’s. The deuterated MILC-TFT’s also have better reliability than the hydrogenated MILC-TFT’s. Finally, a degradation model of donor-like trap states near the drain region is qualitatively proposed to explain the surprising improvement in OFF-state characteristics for MILC-TFT’s after hot-carrier stress.

Chapter 1 Introduction
1.1 General Background and Motivation 1
1.2 Thesis Organization 6
Chapter 2 New Structure Development for Low Temperature Processed Poly-Si Thin-Film Transistors
Part I Improved I-V Characteristics of Polysilicon Thin Film Transistors with Novel Dual-Buffer Drain Structure
2.1 Introduction 10
2.2 Experimental Details 11
2.3 Results and Discussion 12
2.3.1 OFF-Current 12
2.3.2 High Voltage Operation 17
2.4 Summary 18
Part II The Application of Charged Liquid-Phase Deposited Oxide as Interlayer for Self-Induced Lightly-Doped-Drain (SI-LDD) Poly-Si TFT's
2.5 Introduction 20
2.6 Fabrication and Characterization of the Charged LPD SiO2 21
2.7 Fabrication of The SI-LDD Poly-Si TFT’s 21
2.8 Characteristics of The SI-LDD Poly-Si TFT's 22
2.9 Reliability of The SI-LDD Poly-Si TFT's 24
2.10 Summary 24
Chap 3 Highly Reliable Liquid-Phase Deposited SiO2 with Nitrous Oxide Plasma Post-Treatment for Low Temperature Processed Poly-Si TFT’s
3.1 Introduction 49
3.2 Experimental
3.2.1 Preparation of LPD-SiO2 50
3.2.2 Analysis of N2O-Plasma Post-Annealed LPD Oxide 51
3.2.3 Fabrication of LTP N-Channel Poly-Si TFTs 52
3.3 Results and Discussion
3.3.1 Characteristics of N2O-Plasma Post-Annealed LPD Oxide
3.3.1.1 Physicochemical Characteristics 53
3.3.1.2 Electrical Characteristics 57
3.3.1.3 Comparison with N2O-Plasma Oxidation Films 62
3.3.2 Characteristics of LTP Poly-Si TFTs with N2O-Plasma Post-Annealed LPD Gate Oxide
3.3.2.1 Electrical Characteristics 64
3.3.2.2 Defect Passivation Mechanism 67
3.3.2.3 Electrical Reliability 69
3.3.2.4 Gate Oxide Reliability 70
3.4 Summary 71
Chapter 4 Performance and Reliability Improvement of Low Temperature Processed Poly-Si TFT’s with with D2-Plasma Followed by N2O-Plasma Passivation
4.1 Introduction 98
4.2 Experiment Details 99
4.3 Results and Discussion 101
4.3.1 Electrical Characteristics of Poly-Si TFT’s with D2-Plasma Passivation 101
4.3.2 Reliability Analysis of Poly-Si TFT’s with D2-Plasma Passivation 102
4.3.3 Electrical Characteristics of Poly-Si TFT’s with D2-N2O-Plasma Passivation 105
4.3.4 Reliability Analysis of Poly-Si TFT’s with D2-N2O-Plasma Passivation 106
4.4 Summary 108
Chapter 5 Superior Device Performance and Deuterium-Plasma Reliability in Low Temperature Metal-Induced Laterally Crystallized (MILC) Poly-Si TFT's
5.1 Introduction 132
5.2 Device Fabrication 133
5.3 Results and Discussion 134
5.3.1 MILC-TFT Performance 134
5.3.2 Novel U-Shape MILC-TFT 138
5.3.3 Deuterium-Plasma Reliability 138
5.4 Summary 143
Chapter 6 Conclusions
6.1 Conclusions 159
6.2 Future Works 161
References  163
Publications  184

Chapter 1
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Chapter 2
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Chapter 3
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Chapter 4
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Chapter 5
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