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研究生:林千惠
研究生(外文):Chien-Huei Lin
論文名稱:寬頻分碼多重擷取系統之全數位MMSE多使用者接收機:演算法及其FPGA實現
論文名稱(外文):An all digital MMSE Multi-user Receiver for W-CDMA:Algorithm and Its FPGA Implementation
指導教授:吳文榕
指導教授(外文):Wen-Rong Wu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:95
中文關鍵詞:寬頻分碼多重擷取多使用者偵測部分平行干擾消除部分消除因子碼追蹤迴路
外文關鍵詞:W-CDMAmulti-user detectionpartial PICPCFcode tracking loop
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部分平行干擾消除(partial PIC)是一個簡單但有效率的多使用者偵測
(multi-user detection) 的方法,對部分平行干擾消除來說,部分消除因子(PCF)是一個重要的影響因素,通常都是利用嘗試錯誤的方式找到最佳的PCF值。在本篇論文中,我們提出一個適用於寬頻分碼多重擷取(W-CDMA)系統的兩級最小均方差(MMSE)多使用者接收機,利用MMSE的運算法則可以導出最佳的PCF值。在模擬的結果中顯示出,使用所推導出的PCF值可以改善偵測的效能,另外配合使用碼追蹤迴路(code tracking loop)可以讓多使用者接收機更完整。最後,以FPGA的設計流程實現所提出來的低複雜度接收機。

The partial parallel interference cancellation (PIC) is known to be a simple yet effective multi-user detection scheme. However, the partial cancellationfactors (PCF), being critical to the partial PIC, are usually obtained by trial and error. In this thesis, a two-stage minimum mean square (MMSE) partial PIC for the W-CDMA system is proposed. Using the scheme, the optimal PCFs can be theoretically derived. It is shown that the detection can be greatly enhanced using the derived PCFs. The code tracking loop can be incorporated into the partial PIC structure and this results in a complete mutli-user receiver. Finally, a low complexity receiver architecture is proposed and implemented using a FPGA design flow.

Contents
Abstract.....................................................i
摘要.........................................................ii
Acknowledgements ............................................iii
Contents ....................................................iv
List of Figures............................................. vii
List of Tables...............................................x
CHAPTER 1....................................................1
Introduction.................................................1
CHAPTER 2....................................................4
Introduction to Wideband CDMA Systems........................4
2.1 Introduction.............................................4
2.2 Transport Channel........................................6
2.3 Uplink Physical Channel..................................8
2.3.1 Dedicated Uplink Physical Channel .....................9
2.3.2 Common Uplink Physical Channel.........................11
2.4 Code Generation and Allocation...........................12
2.4.1 Scrambling Code........................................12
2.4.2 Channelization Code....................................15
2.5 Uplink Spreading and Modulation..........................16
CHAPTER 3....................................................20
DS/CDMA Systems and Multi-user Detection ....................20
3.1 DS/CDMA Techniques ......................................20
3.2 Synchronization in DS/CDMA Systems.......................22
3.3 Conventional Receiver....................................23
3.4 Multi-user Detection ....................................26
3.4.1 Optimal Detector.......................................27
3.4.2 De-correlating Detector ...............................28
3.4.3 Minimum Mean-Squared Error (MMSE) Detector ............28
3.4.4 Successive Interference Cancellation Detector (SIC)....29
3.4.5 Parallel Interference Cancellation Detector (PIC) .....30
CHAPTER 4....................................................34
An MMSE Partial PIC for Multi-user Detection for W-CDMA .....34
4.1 System Model ............................................34
4.2 A MMSE Partial PIC Detector..............................35
4.2.1 Simple Example Case ...................................35
4.2.2 General Case .........................................40
4.3 Simulation ..............................................43
CHAPTER 5....................................................61
Hardware Design .............................................61
5.1 Design Flow..............................................61
5.2 Hardware System Model....................................62
5.3 Simulation ..............................................68
5.4 Functional Blocks .......................................74
5.4.1 Complex-Valued Multiplier .............................74
5.4.2 Pulse Shaping Filter ..................................74
5.4.3 Chip Matched Filter ...................................76
5.4.4 Interpolation Filter ..................................79
5.4.5 Modified Noncoherent DLL ..............................83
5.4.6 Adder..................................................83
5.5 FPGA Implementation .....................................85
CHAPTER 6....................................................92
Conclusion ..................................................92
Reference ...................................................93

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