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研究生:廖明凱
研究生(外文):Ming-Kai Liao
論文名稱:cdma2000接收機之DSP實現
論文名稱(外文):DSP Implementation of a cdma2000 Receiver
指導教授:張文鐘
指導教授(外文):Wen-Thong Chang
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:63
中文關鍵詞:數位接收機DSP實現
外文關鍵詞:cdma2000DSP
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在這篇論文中,使用德儀(TI)出產的TMS320C6201定點數位信號處理器來實現cdma2000接收機。其中一顆處理器用來實現碼擷取(code acquisition)系統,其中最主要的部分為複數匹配濾波器(matched filter)之運算。在擁有六道多路徑Rayleigh衰減且最大延遲時間為八個切片時間的通道環境下,使用一個擁有128階係數的複數匹配濾波器來和接收到的信號匹配。這個濾波器的各階係數即為接收機端所產生且和接收信號所對應的PN碼。搜尋的不確定區域(uncertainty range)為25 個切片(100 個取樣點)且每隔0.25個切片 (1個取樣點) 做一次搜尋。為了平行運算求出相關值,匹配濾波器的每一個係數均和接收信號中所對應的100個樣本同時相乘,然後再將128個乘積加起來。最後,I和Q通道再平方合併成為複數匹配濾波器的輸出。為了要減少錯誤偵測,我們把連續三個連續的相關值平均作為最後的輸出,而延遲估計器便根據這個結果來估計RAKE接收機中每個finger所對應的PN碼延遲。
另一顆處理器則用來實現碼追蹤(code tracking)系統、通道估計(channel estimation)、despreading、demodulation、RAKE combining和資料決策(data decision)。這顆處理器大部分的計算量都花在通道相位的估計上。在這段計算之中,其實70%的計算量還是在於求平方及和開根號的運算。因此和TDMA系統接收機比起來,cdma2000 接收機的總計算量大約為其1.5倍。

In this thesis, the TI’s TMS320C6201 fixed-point processing nodes are utilized to implement a cdma2000 receiver. One is utilized to implement the code acquisition system, and the most important part of this system is the computing process of the complex multiply matched filter. Under the environment of the multipath static Rayleigh fading channel with 6 paths and the maximal delay spread is 8 chips, a complex multiply matched filter with the length of 128 tap coefficients is used to correlate the received signal. The tap coefficients of this matched filter are the chip values of the corresponding locally generated PN code. The uncertainty range is 25 chips (100 samples) and the searching step is 0.25 chip (1 sample). In order to achieve parallel correlation, each tap of the matched filter is multiplied with the corresponding 100 samples of the received signal, then the resulting 128 products are summed. Finally, the 100 output values corresponding to I and Q branches are squared and summed, and then are treated as the correlation output of the complex multiply matched filter. Besides, 3 continuous blocks of the data are processed each time in order to reduce the false alarm probability. Hence, the 3 outputs of the matched filter corresponding to each block are averaged. According to these results, the delay estimator estimates the corresponding PN code delay of each finger in the RAKE receiver.
The other node is utilized to implement the code tracking system, channel estimation, complex despreading, demodulation, RAKE combining and data decision. Most of the computing power of this processing node is spend for the estimation of the channel phase. During the processing procedure, actually 70% of the computing power is spend for calculating the square and square root. Therefore, compare with the TDMA system which doesn’t include a code acquisition system, a cdma2000 receiver spends about 1.5-times the computing power over the TDMA receiver as a while.

1 Introduction
1.1 Overview of cdma2000 RTT
1.2 Evolution of Radio Interface Technology
1.3 Comparison between CDMA2000 and W-CDMA
2 System and Channel Description
2.1 Transmitter Model
2.1.1 Scrambling Code
2.1.2 Walsh Function for Reverse Dedicated Channels
2.1.3 Baseband Pulse Shaping Filter
2.2 Channel Model
2.3 Receiver Model
2.3.1 Waveform Chip Matched Filter
2.3.2 Synchronization System
2.3.3 RAKE Receivers
3 Code Acquisition System
3.1 Serial-Search Code Acquisition System
3.1.1 Decision of the Length of the Complex Multiply Matched Filter
3.1.2 Decision of the Number of the Blocks
3.2 Delay Estimator
3.3 Performance Analysis
4 DSP Implementation of a cdma2000 Receiver and Detailed Discussions
4.1 Barcelona CompactPCI Board
4.1.1 Bus Architecture and Resources
4.1.2 Memory Map
4.1.3 Data Transfers Between Processor Nodes
4.2 Extended I/O Module
4.2.1 PMC-2MAI Dual 65 MHz 10-Bit ADC Module
4.2.2 PEM-4WDC Wideband Down-Converter
4.3 General DSP Implementation Considerations
4.4 Software Development Environment
4.5 DSP Implementation of a cdma2000 Receiver over Two CPUs
4.5.1 Data Flow
4.5.2 Operation Procedures
4.5.3 Scheduling and Buffer Assignment
4.6 Performance Analysis and Discussions
4.6.1 Memory Usage
4.6.2 System Efficiency
5 Conclusion and Further Work
Bibliography
Vita

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