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研究生(外文):Yung-Zong Cheng
論文名稱(外文):Design of All Digital IF-to-Baseband Up/Down Converter for the IEEE 802.11a WLAN
指導教授(外文):Chia-Chi HungSau-Gee Chen
外文關鍵詞:half-band filterconstellation RMS erroradder tree
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本篇論文將對適用於IEEE802.11a系統中的升降頻轉換器 (Up/Down Converter) 設計做逐一的探討研究。其中所使用的系統之理論,我們採用半頻帶濾波器 (Half-band filter) 之架構及多速率設計其所使用之多相拆解方式。基於多速率系統理論利用內插 (Interpolation) 我們可以一方面將基頻訊號的取樣頻率上升四倍,在另一方面同時在接收端作為ADC後級的降頻濾波器,則利用 (Decimation) 將ADC的輸出訊號之取樣頻率降為四分之一倍。在升降頻的同時,則運用移時 (time shift) 與移頻的原理作基頻訊號與低中頻帶 (Low IF) 之間之轉換。
我們同時希望此一升降頻轉換器能在硬體方面加以實現,因此本篇論文也將硬體架構加以分析。我們藉由一種特別的數碼表示方式 (number representation)及高速率壓縮單元 (high-rate compressor) 來降低硬體的功率消耗與電路複雜度。再利用交錯式的方式濾波器在架構上化簡,達到濾波器資源共享來降低硬體成本。

In this paper, an alternative approach for the design of an IEEE 802.11a standard digital IF up/down converter is presented. The signal up or down conversion are achieved by integrating half-band filter architecture with polyphase decomposition technique used in multi-rate signal processing. According to multi-rate system theory, while on the one hand, the signal sampling frequency can be increased four times by interpolation, on the other hand, the ADC output signal sampling frequency can be decreased four times by decimation. At the same time, we apply the theory of time shift and frequency shift to realize the conversion between baseband and low IF.
This paper also addresses efficient implementation of the up/down converter architecture. By means of an unconventional number representation and high-rate compressor, the power consumption and the complexity of circuits can be decreased significantly. Furthermore, applying the interleaving method to simplify the structure, better resource sharing can be achieved and accordingly the implementation cost can be reduced.

中文摘要 i
英文摘要 ii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 緒論…………………………………………………………….1
1.1 前言 1
1.2 研究動機 2
1.3 升降轉換器的目的 3
1.4 論文章節編排 5
第二章 IEEE802.11a 無線區域網路簡介……………………………..6
2.1 IEEE 802.11a無線區域網路簡介 6
2.2 正交分頻多工特性 10
2.3 IEEE 802.11a調變-解調器 12
2.4 全數位升降頻轉換器 15
第三章 設計升降頻轉換器……………………………………………16
3.1 簡介 16
3.2 多速率系統的基礎 17
3.2.1 Noble Identity 17
3.2.2 多相分解表示 18
3.2.3 半頻帶濾波器 21
3.3 升降頻轉換器之原理 22
3.3.1 降頻轉換 22
3.3.2 升頻轉換 24
3.4 轉換器設計要求 27
3.4.1 線性相位 27
3.4.2 半頻帶濾波器之參數 28
3.4.3 星狀圖均方根誤差 28
3.4.4 通帶濾波設計 29
3.5 半頻帶濾波器設計 31
3.5.1 最小平方誤差設計 31
3.5.2 最佳化設計 31
3.5.3 頻率響應遮敝法 (FRM) 設計 32
3.5.4 以FRM設計半頻帶濾波器 34
3.5.5 合成 36
3.6 合成結果與比較 43
3.6.1 合成結果 43
3.6.2 比較 47
第四章 積體電路VLSI設計………………………………………….51
4.1 簡介 51
4.2 系統架構與設計流程 52
4.2.1 系統架構 52
4.2.2 我們的設計流程 55
4.3 VLSI設計 57
4.3.1 介紹低功率設計 57
4.3.2 在演算法層次上減少運算次數 60 係數乘法結構 60 有號數延伸結構 61 加法結構 68
4.3.3 使用壓縮器降低切換之動作量 72
4.3.4 交錯式的方法 75
4.4 功能模擬與實體合成 77
4.4.1 功能模擬 77
4.4.2 實體合成 77
4.5 比較其它相似的設計 80
第五章 結論……………………………………………………………81
參考文獻 83

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