跳到主要內容

臺灣博碩士論文加值系統

(75.101.211.110) 您好!臺灣時間:2022/01/26 13:28
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:鄭淵綜
研究生(外文):Yung-Zong Cheng
論文名稱:IEEE802.11a無線區域網路全數位中頻至基頻升降頻轉換器之設計
論文名稱(外文):Design of All Digital IF-to-Baseband Up/Down Converter for the IEEE 802.11a WLAN
指導教授:黃家齊黃家齊引用關係陳紹基陳紹基引用關係
指導教授(外文):Chia-Chi HungSau-Gee Chen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:85
中文關鍵詞:半頻帶濾波器星狀均方根誤差加法樹
外文關鍵詞:half-band filterconstellation RMS erroradder tree
相關次數:
  • 被引用被引用:0
  • 點閱點閱:302
  • 評分評分:
  • 下載下載:60
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文將對適用於IEEE802.11a系統中的升降頻轉換器 (Up/Down Converter) 設計做逐一的探討研究。其中所使用的系統之理論,我們採用半頻帶濾波器 (Half-band filter) 之架構及多速率設計其所使用之多相拆解方式。基於多速率系統理論利用內插 (Interpolation) 我們可以一方面將基頻訊號的取樣頻率上升四倍,在另一方面同時在接收端作為ADC後級的降頻濾波器,則利用 (Decimation) 將ADC的輸出訊號之取樣頻率降為四分之一倍。在升降頻的同時,則運用移時 (time shift) 與移頻的原理作基頻訊號與低中頻帶 (Low IF) 之間之轉換。
我們同時希望此一升降頻轉換器能在硬體方面加以實現,因此本篇論文也將硬體架構加以分析。我們藉由一種特別的數碼表示方式 (number representation)及高速率壓縮單元 (high-rate compressor) 來降低硬體的功率消耗與電路複雜度。再利用交錯式的方式濾波器在架構上化簡,達到濾波器資源共享來降低硬體成本。

In this paper, an alternative approach for the design of an IEEE 802.11a standard digital IF up/down converter is presented. The signal up or down conversion are achieved by integrating half-band filter architecture with polyphase decomposition technique used in multi-rate signal processing. According to multi-rate system theory, while on the one hand, the signal sampling frequency can be increased four times by interpolation, on the other hand, the ADC output signal sampling frequency can be decreased four times by decimation. At the same time, we apply the theory of time shift and frequency shift to realize the conversion between baseband and low IF.
This paper also addresses efficient implementation of the up/down converter architecture. By means of an unconventional number representation and high-rate compressor, the power consumption and the complexity of circuits can be decreased significantly. Furthermore, applying the interleaving method to simplify the structure, better resource sharing can be achieved and accordingly the implementation cost can be reduced.

中文摘要 i
英文摘要 ii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 緒論…………………………………………………………….1
1.1 前言 1
1.2 研究動機 2
1.3 升降轉換器的目的 3
1.4 論文章節編排 5
第二章 IEEE802.11a 無線區域網路簡介……………………………..6
2.1 IEEE 802.11a無線區域網路簡介 6
2.2 正交分頻多工特性 10
2.3 IEEE 802.11a調變-解調器 12
2.4 全數位升降頻轉換器 15
第三章 設計升降頻轉換器……………………………………………16
3.1 簡介 16
3.2 多速率系統的基礎 17
3.2.1 Noble Identity 17
3.2.2 多相分解表示 18
3.2.3 半頻帶濾波器 21
3.3 升降頻轉換器之原理 22
3.3.1 降頻轉換 22
3.3.2 升頻轉換 24
3.4 轉換器設計要求 27
3.4.1 線性相位 27
3.4.2 半頻帶濾波器之參數 28
3.4.3 星狀圖均方根誤差 28
3.4.4 通帶濾波設計 29
3.5 半頻帶濾波器設計 31
3.5.1 最小平方誤差設計 31
3.5.2 最佳化設計 31
3.5.3 頻率響應遮敝法 (FRM) 設計 32
3.5.4 以FRM設計半頻帶濾波器 34
3.5.5 合成 36
3.6 合成結果與比較 43
3.6.1 合成結果 43
3.6.2 比較 47
第四章 積體電路VLSI設計………………………………………….51
4.1 簡介 51
4.2 系統架構與設計流程 52
4.2.1 系統架構 52
4.2.2 我們的設計流程 55
4.3 VLSI設計 57
4.3.1 介紹低功率設計 57
4.3.2 在演算法層次上減少運算次數 60
4.3.2.1 係數乘法結構 60
4.3.2.2 有號數延伸結構 61
4.3.2.3 加法結構 68
4.3.3 使用壓縮器降低切換之動作量 72
4.3.4 交錯式的方法 75
4.4 功能模擬與實體合成 77
4.4.1 功能模擬 77
4.4.2 實體合成 77
4.5 比較其它相似的設計 80
第五章 結論……………………………………………………………81
參考文獻 83

[1] R. Pasko., L. Rijnders, Schaumont, P.R. Vernalde, S.A. Durackova,and D. “High-performance flexible all-digital quadrature up and down converter chip,” IEEE J. Solid-State Circuits, Vol. 36, Mar. 2001, pp. 408 —416
[2] T. Hwntschel and G. Fettweis, “Sample rate conversion for software radio,” IEEE comm. Mag. Aug. 2000, pp.142-150
[3] A. K. Ong, and B. W. A. Wooley, “A two-path bandpass delta-sigma modultor for digital IF extraction at 20 Mhz,” IEEE J. Solid-State Circuits, Vol. 32, Dec 1997, pp. 1920 —1934
[4] L. K. Tan and H. Samulie, “A 200 Mhz quadrature digital synthsizer/mixer in 0.8-um CMOS,” IEEE J. Solid-State Circuits, Vol. 30, Mar. 1995, pp. 193 —200
[5] E. B. Hogenauer, “An economical class of digital filter for decimation and interpolation,” IEEE Trans. ASSP Vol. ASSP-29, Apr. 1981, pp.155-162
[6] A. Y. Kwentus, Z. Jiang and A. N. Willson, “Application of filter sharpening to cascaded integrator- comb decimation filter,” IEEE Trans. Signal Processing Vol.45, Feb. 1997, pp.475-467
[7] H.J. Oh,., K. Sunbin, C. Ginkyu and Y.H Lee, “On the use of interpolated second-order polynomials for efficient filter design in programmable downconversion,” IEEE J. Selected Areas in Communications, Vol.17, Apr.1999, pp. 551-560
[8] M. Faulkner, “The effect of filtering on the performance of OFDM systems,” IEEE Trans. Vehicular Technology, Vol. 49 , Sept. 2000, pp. 1877 —1884
[9] D. B. Chester, “Digital IF filter technology for 3G system: an introduction,” IEEE comm. Mag. Feb. 1999, pp.102-107
[10] Marcos Martinez-Peiro and Lar Wanhammar, “High speed, low complexity fir filter using multiplier block reduction and polyphase decomposition,” ISCAS, May. 2000, pp367-370
[11] Xiaodong Li; Cimini, L.J., Jr., “Effects of clipping and filtering on the performance of OFDM,” IEEE Communications Letters, Vol. 2, May 1998, pp. 131 —133
[12] T. H. Lee, H. Samavati, and H. R. Rategh, “5-GHz CMOS wireless LANs,” IEEE Trans. on microwave theory and techniques, vol 50, Jan. 2002, pp268-280
[13] IEEE P802.11a, Part 11: Wireless LAN MAC and PHY Specifications: High Speed Physcial Layer in the 5GHz band, 1999.
[14] Nati Dinur and Dov Wulich, “Peak-to-Average Power Ratio in High-Order OFDM,” IEEE Trans. on communications, vol. 49, Jun. 2001, pp1063-1072
[15] R. E. Crochiere and L. R. Rabiner, Multirate Digital Signal Processing. Englewood Chiffs, NJ: Prentice-Hall, 1983
[16] P. P. Vaidyanathan, Multirate Systems and Filter Banks. Englewood Chiffs, NJ: Prentice-Hall, 1983
[17] L. B. Jackson, Digital Filter and Signal Processing. Hingham, MA: Kluwer Academic, 1995
[18] J. Vankka, M. Kosunen, I. Sanchis, Halonen, K.A.I., “A multicarrier QAM modulator,” IEEE Trans. on Circuits Syst. II, Vol. 47, Jan. 2000, pp. 1 —10
[19] J. Laskowski, and H Samueli, “A 150-mhz 43-tap half-band FIR digital filter in 2-/spl mu/m CMOS generated by silicon compiler,” Custom Integrated Circuits Conference, 1992., IEEE Proc., pp.11.4.1 -11.4.4
[20] Y.C. Lim, “Frequency-response masking approach for the synthesis of sharp linear phase digital filter,” IEEE Trans. on Circuits Syst. II. Vol. 33, Apr. 1986, pp. 357 -364
[21] L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing. Englewood Chiffs, NJ: Prentice-Hall, 1975
[22] P. P. Vaidyanathan, and T. Q. Nguyen, “A trick for the design of FIR half-band filters,” IEEE Trans. on Circuits and Systems, vol. CAS-34, Mar. 1987, pp734-738
[23] Saramaki, T., Y.C. Lim, and Yang, R., “The synthesis of half-band filter using frequency-response masking technique,” IEEE Trans. on Circuits Syst. II, Vol. 42, Jan. 1995, pp. 58 —60
[24] A.P. Chandrakasan, and R.W. Brodersen, “Minimizing power consumption in digital CMOS circuits,” IEEE Proc. Vol. 83 , Apr. 1995, pp. 498 -523
[25] R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE J. Solid-State Circuits, Vol. 32, Jul 1997, pp. 1079 —1090
[26] H. Samueli, “An improved search algorithm for the design of multiplierless FIR filters with powers of two coefficients,” IEEE Trans. on Circuits Syst. II, Vol. 36, July. 1989, pp. 1044 —1047
[27] R. Pasko., L. Rijnders, Schaumont, P.R. Vernalde, S.A. Durackova,and D. “High-performance flexible all-digital quadrature up and down converter chip,” IEEE J. Solid-State Circuits, Vol. 36, March 2001, pp. 408 —416
[28] K.K Parhi, “VLSI digital signal processing systems :design and implementation,” New York, Wiley,1999
[29] M. Nagamatsu, et.al., “A 15ns 32x32b CMOS multiplier with an improved parallel structure,” Proc. 1989 CICC pp.103.1-103.4
[30] V.G. Moshnyaga and K. Tamaru, “A comparative study of switching activity reduction techniques for design of low-power multipliers,” IEEE Circuits Syst. International Symp, Vol.3, 1995, pp1560 -1563
[31] Larsson, P. and Nicol, C.J., “Transition reduction in carry-save adder trees,” Low International Symp. Power Electronics and Design, 1996, pp. 85 -88
[32] Zhongnong Jiang and A.N., Jr Willson, “Efficient digital filtering architectures using pipelining/interleaving,” IEEE Trans. on Circuits Syst. II, Vol. 44, Feb. 1997, pp. 110 —119
[33] T. Yoshino,.H. Davis, A. Shah, P. Yang, and R. Jain, “A 100 MHz 64-tap FIR digital filter in a 0.8 mu m BiCMOS gate array,” ISSCC Digest of Technical Papers. pp.1990 114 —115,Feb. 1990
[34] G. L. Do and K. Feher, “Efficient filter design for IS-95 CDMA filter,” IEEE Trans on Consumer Electronic, Vol. 42, No4, Nov. 1996 pp. 1011-1020

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top