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研究生:李庭怡
研究生(外文):Ting-Yi Lee
論文名稱:雜湊函數sha-1之硬體設計與實現
論文名稱(外文):Hardware design and implementation of hash function SHA-1
指導教授:李程輝
指導教授(外文):Tsern-Huei Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:46
中文關鍵詞:雜湊函數SHA-1硬體
外文關鍵詞:SHA-1hardware implementation
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用於網路安全機制的密碼演算法其運算處理速度在近年來的研究領域中越來越受到重視。然而,過去的研究成果顯示出以軟體設計實現的架構不論在加解密或是認證方面其效能可謂相當低落,以至於無法滿足現實環境的需要。近年來越來越多的跡象顯示網路安全的應用架構(如,企業內部虛擬網路)其高速處理密碼演算加速器日益受到重視以及關注。因此,在這篇論文中我們將顯示,建構一個以硬體為設計與實現基礎的密碼演算法加速器(如HMAC賴以為基礎的雜湊函數SHA-1)是合理且必要的。我們所提出的”五組內部平行執行單元組”的嶄新架構將提供雜湊函數SHA-1極佳的效能,其表現與現今商用產品不惶多讓。

The processing speed of cryptographic algorithms in IP Security (IPSec) has received much attention in recent research, and it has been shown that software design and implementation performs poorly in either encryption or authentication. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as Virtual Private Networks (VPN). Hence, as we shall show in this thesis, it’s necessary and reasonable to construct cryptographic accelerators using hardware design and implementation of HMACs based on a hash algorithm such as SHA-1. The novel architecture we proposed, five internal parallel-execution entities, leads to a supreme performance as well as the commercial products nowadays.

CHAPTER1. INTRODUCTION
1.1 HASH FUNCTIONS
1.2 FPGA IMPLEMENTATION
CHAPTER2. SECURE HASH ALGORITHM, SHA-1
2.1 SHA-1
2.2 SHA-1 LOGIC
2.3 SHA-1 COMPRESSION FUNCTION:
2.4 SHA-1 WORD PROCESSING
CHAPTER3. PRELIMINARY ANALYSIS
3.1 PARALLEL ARCHITECTURE
3.2 CRITICAL PATH ANALYSIS
3.3 PRIMITIVE FUNCTION FT IN THE CRITICAL PATH
3.4 WORD PROCESSING
CHAPTER4. HARDWARE IMPLEMENTATION ARCHITECTURE
4.1 METHODOLOGY AND TOOLS
4.2 OVERVIEW OF SHA-1 CORE ENGINE
4.3 ITERATIVE LOOPING ARCHITECTURE
4.3 SHA-1 FSM
4.4 CORE FUNCTION MODULE
4.5 WORD PROCESSING MODULE
4.6 RTL NETLIST
CHAPTER 5 PERFORMANCE EVALUATION
5.1 FPGA PERFORMANCE COMPARISON
5.2 ASIC PERFORMANCE COMPARISON
CHAPTER 6. CONCLUSION

[BGV96] Antoon Bosselaers, René Govaerts and Joos Vandesalle, “Fast hashing on the Pentium”, Advances in Cryptology, Proceedings Crypto ’96, LNCS1109, N. Koblitz, Ed., Springer-Verlan, 1996, pp. 298-312.
[BGV97] Antoon Bosselaers, René Govaerts and Joos Vandesalle, “SHA: A Design for parallel Architectures?” Advances in Cryptology, Proceedings Eurocrypt ’97, LNCS 1233, W. Fummy, Ed., Springer-Verlag, 1997, pp. 348-362.
[DHV01] J. Deepakumara, H. M. Heys, and R. Venkatesan, “FPGA Implementation of MD5 Hash Algorithm ”, Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), May 2001.
[FIPS180-1] FIPS 180-1, “Secure hash standard”, US Department of Commerce/NIST, Washington D.C., April 1995.
[Pal96] S. Palnitkaf, Verilog HDL, A guide to digital design and synthesis. Upper Saddle River, NJ: Prentice Hall, 1996.
[Stal99] W. Stallings, Cryptography and network security-principles and practice, second edition. Upper Saddle River, NJ: Prentice Hall, 1999.
[Tho98] D. Thomas & P. Moorby, The Verilog® hardware description language, fourth edition. Kluwer Academic Publishers, 1998.
[Helion] Helion Technology Limited. Web Site: http://www.heliontech.com
[SecuCore] SecuCore Consulting Services. Web Site: http://www.secucore.com
[CAST] CAST, Inc. Web Site: http://www.cast-inc.com
[Ocean] Ocean Logic Pty Ltd. Web Site: http://www.ocean-logic.com
[ALMA] ALMA Technologies. Web Site: http://www.alma-tech.com
[SCI-WORX] SCI-WORX GmbH. Web Site: http://www.sci-worx.com
[HDL] HDL Design House. Web Site: http://www.hdl-dh.com

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