跳到主要內容

臺灣博碩士論文加值系統

(54.83.119.159) 您好!臺灣時間:2022/01/17 10:06
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:許民傑
研究生(外文):MIN-CHIEH Hsu
論文名稱:1.8GHzDCS-1800金氧半射頻頻率合成器的設計
論文名稱(外文):The Design of A 1.8GHz CMOS RF Frequency Synthesizer for DCS-1800 Application
指導教授:高曜煌
指導教授(外文):Yao-Huang Kao
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:76
中文關鍵詞:金氧半DCS-1800壓控振盪器正單相時脈電路電感相位雜訊分數式頻率合成器
外文關鍵詞:CMOSDCS-1800VCOTSPCinductorphase noisefractional-Nfrequency synthesizer
相關次數:
  • 被引用被引用:3
  • 點閱點閱:134
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文中實現一個具有頻率的準確度和解析度的內含單晶LC金氧半壓控振盪器的射頻頻率合成器。金氧半壓控振盪器的架構為互補式雙交叉耦合對(complementary cross-coupled pair),並使用積體式電感電容共振調諧電路,將電感的線寬最佳化,以提升品質因素﹝Quality Factor﹞。另外提出一個設計低雜訊壓控振盪器的流程,以及一個準確預估相位雜訊的方法。對於預除器的設計,採用正單相時脈電路的D型正反器並結合邏輯閘,以減小延遲達到快速的目的。最後提出一個0.35μm符合DCS-1800規格的分數式射頻頻率合成器,可以涵蓋發射頻率和接收頻率1.728GHz~1.824GHz和1.782GHz~1.881GHz,相位雜訊在600KHz和3MHz分別是-120.1dBc/Hz以及-134.3dBc/Hz。
Phase-locked loop (PLL) based fractional-N frequency synthesizers have played an important role in RF front-ends. The purpose of this work is to implement a RF frequency synthesizer with a monolithic LC-tank voltage-controlled oscillator (VCO). The architecture of VCO is complementary cross-coupled pairs. The Quality factor of the on-chip spiral inductor is optimized by varying the metal width in each turn. A procedure of designing a low phase noise oscillator is provided. And the prediction of phase noise is also indicated. High-speed dual-modulus prescaler is implemented by merging the so-called True Single-Phase Clock (TSPC) D flip-flops (DFFs) as well as logic gates to reduce propagation delay. Finally, the fractional-N frequency synthesizer for DCS-1800 application is implemented in 0.35μm CMOS technology. The synthesized frequency is 1.728GHz to 1.824GHz and 1.782GHz to 1.881GHz for TX and RX, respectively. The phase noise is -120.1dBc/Hz @600KHz and -134.3dBc/Hz @3MHz.
CHINESE ABSTRACT i
ENGLISH ABSTRACT ii
ACKNOWLEDGEMENTS iii
CONTENTS iv
TABLE CAPTIONS vi
FIGURE CAPTIONS vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Specifications 2
1.3 Frequency Synthesizer Architecture 3
1.3.1 PLL Fundamentals 3
1.3.1.1 Basic PLL 4
1.3.1.2 Charge-Pump PLL 6
1.3.2 Frequency Synthesis 8
1.3.2.1 Integer-N synthesis 8
1.3.2.2 Fractional-N synthesis 9
1.4 Organization of the thesis 14
Chapter 2 Design of the Voltage-Controlled Oscillator 15
2.1 On-chip Spiral Inductors Design 15
2.1.1 Design Guideline 15
2.1.2 Improvement of the Quality Factor of RF Spiral Inductor 16
2.1.3 Fabrication and Measurement 21
2.2 Design and Implementation of VCO with LC tank 22
2.2.1 Simulation, Fabrication and Measurement 22
2.3 Prediction of Phase Noise 37
2.3.1 The Method of Prediction 37
2.3.2 Experiment 39
Chapter 3 Design of the High-Speed Prescaler 42
3.1 High-Speed Prescaler 43
3.1.1 Architecture 43
3.1.2 Circuit Description 46
3.1.2.1 Asynchronous Counter 46
3.1.2.2 Synchronous Counter 47
3.1.2.3 Input Preamplifier Design 48
3.1.3 Simulation Results 48
3.2 Phase Frequency Detector (PFD) 50
3.3 Charge Pump (CP) 52
3.4 Active filter 54
Chapter 4 Design of the RF Frequency Synthesizer 55
4.1 Integer-N Frequency Synthesizer Design 55
4.1.1 System Design 55
4.1.2 Phase Noise Performance Analysis 59
4.1.3 Summary 61
4.2 Fractional-N Frequency Synthesizer Design 63
4.2.1 System Design 63
4.2.2 Phase Noise Performance Analysis 69
4.2.3 Summary 70
Chapter 5 Conclusion and Future Prospect 73
5.1 Conclusion 73
References 74
[1] Li Lin, “Design Techniques for High Performance Integrated Frequency Synthesizers for Multi-standard Wireless Communication Applications,” dissertation of Doctor, University of California, Berkeley, America, Fall, 2000.
[2] T. Stetzler, I. Post, J. Havens, M. Koyama, “A 2.7-4.5V Single Chip GSM Transceiver RF Integrated Circuit,” IEEE JSSC, vol. 30, no. 12, pp. 1421-1429, Dec. 1995.
[3] J. Craninckx and M. Steyaert, “Wireless CMOS Frequency Synthesizer Design,” Kluwer Academic Publishers, Boston, 1998.
[4] B. Razavi, “RF Microelectronics,” Upper Saddle River, NJ: Prentice-Hall, 1998.
[5] J. Yuan and C. Svensson, “High speed CMOS circuit technique,” IEEE JSSC, vol.24, pp.62-70, Feb. 1989.
[6] Kang-Chun Peng, “Field-Programmable Gate-Array Design of Fractional-N Frequency Synthesizer for Wireless Communications,” thesis of NSYSU, Taiwan, R.O.C, pp.7, 2000.
[7] D. Butterfield and B. Sun, “Prediction of Fractional-N Spurs for UHF PLL Frequency Synthesizers,” IEEE MTT-S Symposium on Technologies for Wireless Applications, pp.29-34, 1999.
[8] J. M. Lopez-Villegas, J. Samitier, C. Cane, P. Losantos, and J. Bausells, ”Improvement of the Quality Factor of RF Integrated Inductors by Layout Optimization,” IEEE Transactions on Microwave Theory and Techniques, Vol.48, No.1, January 2000, pp. 76-83.
[9] C. Y. Yang, G. K. Dehng, J. M. Hsu and S. I. Liu, “New dynamic flip-flops for high-speed dual-modulus prescaler,” IEEE JSSC, vol. 33, no. 10, pp. 1568-1571, Oct. 1998.
[10] Chao-Chih Hsiao, and Yi-Jen Chan, “RF Large-Signal Models with 0.35um Process,” NCU, May 20, 2000.
[11] Chia-Ying Lee, “High Q Suspended Spiral Inductors on Silicon and Their Use in a Active Bandpass Filter,” thesis of NCTU, Taiwan, R.O.C, 2000.
[12] Sheng-Min Ke, ”A Fully Integrated Suspended Spiral-LC CMOS VCO with Prescaler,” thesis of NCTU, Taiwan, R.O.C, 2001.
[13] F. Sischka, “Introduction of de-embedding of parasitic components,” HP High-Frequency Device Modeling Technology Workshop, May 1998.
[14] C. K. Chiu, “Design and Realization of CMOS RF Frequency Synthesizer,” thesis of NTU, Taiwan, R.O.C, 2000.
[15] D. Ham and a. Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs” IEEE J. Solid-State Circuits. Vol.36, no. 6, June 2001.
[16] A. Hajimiri and T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators, ” IEEE J. Solid-State Circuits. Vol. 33, no. 2, Feb. 1998.
[17] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE JSSC, vol. 31, no. 3, pp. 331-343, 1996.
[18] A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS oscillators with switched tuning.” Proc. of Custom Integrated Circuits Conference, pp. 555-558, 1998.
[19] D. B. Lesson, “A Simple Model of Feedback Oscillator Noise Spectrum, ” Proc. IEEE, vol. 54, pp. 329-330, Feb. 1966.
[20] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May 1999.
[21] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Company, Inc, 2000.
[22] A. A. Abidi, ”High-frequency noise measurements of FET’s with small dimensions,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1801-1805, Nov. 1996.
[23] N. Foroudi and T. A. Kwasniewski, “CMOS high-speed dual-modulus frequency divider for RF frequency synthesis,” IEEE JSSC, vol. 30, no. 2, pp. 93-100, Feb. 1995.
[24] J. Craninckx and M. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS,” IEEE JSSC, vol. 31, no. 7, pp. 890-897, July 1996.
[25] J. Yuan and C. Svensson, “High-speed CMOS circuits technique,” IEEE JSSC, vol. 24, no. 1, pp. 62-70, Feb. 1989.
[26] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE JSSC, vol. 31, no. 3, pp. 456-465, Mar. 1996.
[27] B. Chang, J. Park, and W. Kim, “ A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flop,” IEEE JSSC, vol. 31, no. 5, pp. 749-752, May 1996.
[28] C. Y. Yang, G. K. Dehng, J. M. Hsu and S. I. Liu, “New dynamic flip-flops for high-speed dual-modulus prescaler,” IEEE JSSC, vol. 33, no. 10, pp. 1568-1571, Oct. 1998.
[29] R. Rogenmoser, Q. Huang, and F. Piazza, “1.57GHz asynchronous and 1.4 GHz dual-modulus 1.2-μm CMOS prescalers,” IEEE 1994 Custom Integrated Circuits Conference, pp. 387-390.
[30] R. Rogenmoser, N. Felber, Q. Huang, and W. Fitchtner, “1.16 GHz dual-modulus 1.2-μm CMOS prescaler,” in Proc. IEEE 1993 CICC, San Diego, CA, May 1993, pp. 27.6.1-27.6.4.
[31] S. H. Yang, C.H. Lee, and K. R. Cho, “A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop,” in Proc. 14th Annual IEEE International, pp.276-280, 2001
[32] R. E Best, Phase-Locked Lops: Theory, Design and Applications, New York: McGraw-Hill, 1984.
[33] J. Craninckx and M. S. J. Steyaert, ”A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE JSSC, vol. 33, pp. 2054-65, Dec. 1998.
[34] J. Alvarez, H. Sanchez, and G. Gerosa, “A wide-band low-voltage PLL for PowerPC microprocessors,” IEEE JSSC, vol. 30, pp. 383-391, Apr. 1995.
[35] C. Lam, and B. Razavi, “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-m CMOS technology,” IEEE JSSC, vol. 35, no. 5, May, 2000.
[36] Pi-An Wu, “CMOS RF Frequency Synthesizers with Quadrature Phase Output,” thesis of NCTU, Taiwan, R.O.C, 2002
[37] Chauo-Min Chen, “Design of Fractional-N Frequency Synthesizer for DCS-1800,” thesis of NCTU, Taiwan, R.O.C, 2002
[38] H.Wolaver, “Phase-Locked Loop Circuit Design,” Prentice-Hall, N. Y. 1991.
[39] A. Lehner, R. Weigel, D. Sewald, H. Eichfeld, A. Hajimiri, “Design of a novel low-power 4th-order 1.7 GHz CMOS frequency synthesizer for DCS-1800,” IEEE International Symposium on Circuits and Systems, vol.5, pp. V-637-V-640, May, 2000.
[40] W. Rhee, B. S. Song A. Ali, “A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-b Third-OrderΔΣModulator,” IEEE J. Solid-State Circuits, vol. 35, pp.1453-1460, Oct. 2000.
[41] “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL’s” National Semiconductor Application Note 1001, July, 2001.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊