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研究生:陳喬民
研究生(外文):Chauo-Min Chen
論文名稱:應用於DCS-1800之分數型頻率合成器設計
論文名稱(外文):Design of Fractional-N Frequency Synthesizer for
指導教授:高曜煌
指導教授(外文):Yao-Huang Kao
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:60
中文關鍵詞:金氧半分數型頻率合成器除法器整數型Σ-Δ調變器
外文關鍵詞:CMOSDCS-1800fractional-Nfrequency synthesizerInteger-NΣ-ΔModulator
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  • 被引用被引用:1
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本論文主要探討整數型(Integer-N)和分數型(Fractional-N)頻率合成器兩者之間的差異性,針對分數型(Fractional-N)頻率合成器設計中,討論分數突波的原因及改善方法,此合成器採用具有快速鎖頻、與低分數突波特性頻率解析度為0.0596 Hz之25位元三階ΣΔ調變器架構及一8模除頻器,並利用可程式陣列邏輯(FPGA)將數位電路加以實現﹔頻率合成器中所要使用到數位電路如相位檢測器、可程式計數器和ΣΔ調變器,亦有詳細設計﹔可程式計數器的設計中,可在結束位元件檢測電路中加上一D型正反器,提高整體工作頻率,並利用TSMC 1p4m 0.35微米金氧半製成加以實現。

In this thesis, a fractional-N frequency synthesizer wih improved fractional spurs is studied. It employed the 25 bits third-order sigma-delta modulator technique to achieve low fast settling time, low fractional spurs and 0.0596 Hz frequency resolution. The third-order sigma-delta modulator as well as eight mode divider are realized on FPGA. The differences performances between Integer-N and fractional-N frequency synthesizer are indicated. The digital circuits such as phase frequency detector, programmable counter and sigma-delta modulator are also designed. The operating frequency of programmable counter is enhanced with extra added a D-flip-flop structure. The programmable counter are fabricated by TSMC 0.35um CMOS 1p4m technology.

中文摘要CHINESE ABSTRACT i
英文摘要ENGLISH ABSTRACT ii
致謝ACKNOWLEDGEMENTS iii
目錄CONTENTS iv
圖表目錄FIGURE &TABLE CAPTIONS vi
第一章 緒論 1
1.1 研究背景和動機
1.2 論文組織 3
第二章 分數型頻率合成器架構與原理 5
2.1鎖相迴路基本原理 5
2.1.1鎖相迴路分析 6
2.1.2鎖相迴路之雜訊分析 10
2.2 計數器分數型頻率合成器設計 13
2.3 ΣΔ(Sigma-Delta)調變器原理分析 16
2.4 一階ΣΔ(Sigma-Delta)調變器架構分析 19
2.5 三階ΣΔ(Sigma-Delta)調變器架構分析 26
第三章 整數型與分數型頻率合成器之設計 35
3.1整數型頻率合成器 35
3.1.1相位檢測器原理與設計 36
3.1.2迴路濾波器之設計 39
3.1.3可程式除頻器原理與設計 41
3.2 分數型頻率合成器中的ΣΔ調變器和多模除頻器之設計與量 49
第四章 結論 56
參考文獻 57

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