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研究生:趙子羽
研究生(外文):Tz-Yu Jau
論文名稱:Triple-DES及AES加密演算法的硬體設計與實現
論文名稱(外文):Hardware Design and Implementation of Triple-DES and AES Algorithms
指導教授:李程輝
指導教授(外文):Tsern-Huei Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:47
中文關鍵詞:加密演算法硬體設計
外文關鍵詞:DESAESFPGA
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隨著網際網路的快速發展,網路安全的課題也日益受到重視。資料加密是提供網路安全的一項重要技術,而Triple-DES是目前最廣泛使用的加密演算法,AES則是用來取代DES的下一代加密演算法。隨著網路傳輸技術的進步,不論何種加密演算法,過去利用軟體提供加密功能的技術,已經無法滿足目前網路的傳輸速度。
在這篇論文中,利用Altera公司的FPGA平台實現Triple-DES及AES加密演算法,並提出一種新的Triple-DES硬體架構,此架構能有效增進目前Triple-DES的處理速度。我們選擇利用FPGA實現的原因在於它較有彈性,可針對不同環境調整不同的架構,並可有效加快加密演算法的處理速度。FPGA結合了硬體處理速度的優點及軟體的彈性,配合不同環境所需的架構作適當調整,可使加密處理滿足寬頻時代的速度要求,同時也能配合不同演算法的產生做適當的調整,有效的滿足實際的需求。
With the rapid growth of the Internet applications, network security becomes as an important issue. Data encryption is one of the essential technologies when implementing the network security. Triple DES is amongst the most widely known, trusted and used nowadays; as to AES, it’s the one that will replace the DES and become as the next generation encryption algorithm. Due to the great progress made by the network transmission technology, software implementation of encryption algorithms in that past decade couldn’t satisfy the high-speed network transmission. Hence, no matter what kind of encryption technologies are adapted, construct cryptographic accelerators using hardware implementation is necessary in the future.
In this thesis, we implement the Triple-DES and AES encryption algorithms via the Altera FPGA board. Besides, we propose a novel hardware architecture implementation of the Triple DES encryption algorithm. This new architecture can increase the processing speed much more than the other commercial ones. The reason why we implement our Triple DES and AES on the FPGA board is its two characteristics: high-processing speed and flexible programming environment. As a result, we could optimize our architectures according to either the algorithm itself or different environment variables and satisfy the demand in reality.
Contents
Chinese Abstract…………………………………………………………………….
……………………………………………………………... i
English Abstract…………………………………………………………………….
……………………………………………………………... ii
Acknowledgement…………………………………………………………………..……..
……………………………………………………………... iii
Contents…………………………………………………………………………….. iv
List of Tables………………………………………………………………………..
……………………………………………………………... Vi
List of Figures……………………………………………………………………….
……………………………………………………………... Vii
Chapter 1 Introduction……………………………………………………………............................................................................................
1
Chapter 2 Triple-DES and AES Algorithm………………………………………
2
2.1 DES — Data Encryption Standard…………………………………... 2
2.1.1 Introduction………………………………………………………….
2
2.1.2 Details of Single Round……………………………………………..
4
2.1.3 Key Schedule……………………………………..............................
5
2.1.4 Decryption……………………………………………………….. 8
2.1.5 DES Variation — Triple-DES………………………………………… 8
2.2 AES-Advanced Encryption Standard…………………………......... 10
2.2.1 Introduction…………………………………………………………. 10
2.2.2 Details of Single Round……………………………………………...
13
2.2.3 Key Expansion……………………………………………………….
17
2.2.4 Cipher……………………………………………………………….. 18
2.2.5 Decipher…………………………………………………………….. 19
2.2.6 Equivalent Inverse Cipher…………………………………………...
20
Chapter 3 Hardware Design and Implementation of Triple-DES and AES…...
……………………….. 23
3.1 Design and Implementation of Triple-DES………………………… 23
3.1.1 Pin Arrangement of Triple-DES……………………………………. 23
3.1.2 Block Diagram of Triple-DES……………………………………… 24
3.1.3 Implementation of DES………………………………………… 26
3.1.4 Timing Diagram……………………………………………....... 28
3.1.5 Implementation Result………………………………………….. 29
3.2 Novel Hardware Design Triple-DES………………………………. 30
3.2.1 Block Diagram of DES………………………………………… 30
3.2.2 Implementation of a Novel DES………………………………... 30
3.2.3 Timing Diagram……………………………………………...... 35
3.2.4 Implementation Result…………………………………………. 35
Chapter 4 Design and Implementation of AES………………………………….. 36
4.1 Pin Arrangement of AES…………………………………………… 36
4.2 Block Diagram of AES……………………………………………... 37
4.3 Round Module……………………………………………................ 38
4.4 KEY Processor……………………………………………............... 41
4.5 Timing Diagram……………………………………………............. 43
4.6 Implementation Result……………………………………………... 44
Chapter 5 Conclusion………………………………………………………………. 46
Reference…………………………………………………………………………….......................................................................................... 47
Reference
[1]. U.S. DEPARTMENT OF COMMERCE/National Institute of Standards and Technology. http://csrc.nist.gov/fips/fips46-3.pdf.
FIPS PUB 46-3: Data Encryption Standard (DES), October 25, 1999.
[2]. Electronic Frontier Foundation. "EFF DES Cracker" machine brings honesty to crypto debate. Press Release, July17, 1998. http://www.eff.org/pub/Privacy/Crypto_misc/DESCracker/HTML/19980716_eff_descracker_pressrel.html.
[3]. Electronic Frontier Foundation. DES Challenge III broken in record 22 hours. Press Release, January 19, 1999. http://www.eff.org/pub/Privacy/Crypto_misc/DESCracker/HTML/19990119_deschallenge3.html
[4]. U.S. DEPARTMENT OF COMMERCE/National Institute of Standards and Technology. Announcing request for candidate algorithm nominations for the Advanced Encryption Standard (AES). World Wide Web, September 12, 1997. http://csrc.nist.gov/encryption/aes/pre-round1/aes_9709.htm.
[5]. U.S. DEPARTMENT OF COMMERCE/National Institute of Standards and Technology. http://www.itl.nist.gov/fipspubs/fip46-2.htm.
FIPS PUB 46-2: Data Encryption Standard (DES), December 30, 1993.
[6]. http://www.cast_inc.com
[7]. http://www.ocean_logic.com
[8]. http://www.tality.com
[9]. http://www.secucore.com
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