臺灣博碩士論文加值系統

氮化鈦薄膜與低介材HSQ應用於
銅金屬製程之性質研究
研究生：鄭淳元 指導教授：龍文安 博士
國立交通大學
應用化學研究所碩士班
摘要
以不同比例之氬與氮為濺鍍氣体，沉積金屬鈦薄膜、不同含量之氮化鈦及鈦/氮化鈦雙層薄膜，另以鈦金屬薄膜在電漿之環境下，通入氮氣進行表面改質。以四點探針、AES、XRD、AFM、SEM、ESCA及應力量測儀分析上述薄膜作為銅擴散阻障層之特性。
在銅/鈦/矽結構中，鈦阻障層厚10奈米，在25℃時，電阻係數為3.8μΩ-cm，於400℃、1小時回火處理後，發現Cu薄膜劣化，Ti阻障層失效，使電阻係數驟升為50.3μΩ-cm。在銅/氮化鈦/矽結構中，700℃回火後，表面有Cu3Si晶體析出。銅/氮化鈦/鈦/矽結構之電阻係數介於銅/氮化鈦/矽結構與銅/鈦/矽結構之間，當N2/Ar流量在6/24 sccm以下時，壓縮應力明顯下降，且其失效溫度可高達700℃。
鈦薄膜經氮電漿改質，發現功率對電阻係數影響最大，有49%η總變異是由功率因子所導致；而時間對表面粗糙度影響最大，有80%η總變異是由時間因子所導致。

The Study on the Properties of TiNx Thin Film and Low-k Material HSQ for Copper Metallization Process
Student: Cheng Chun-yuan Advisor: Dr. Loong Wen-an
Institute of Applied Chemistry, National Chiao Tung University
Abstract
The depositions of Ti, TiNx and TiNx/Ti bilayer thin films with various ratios of argon and nitrogen sputtering gases, and the surface modification of Ti thin film by N2 plasma were achieved. By applying 4-point probe, AES, XRD, AFM, SEM, ESCA and stress measurement system to analyze their properties as Cu diffusion barrier layer.
In the multi-structure of Cu/Ti/Si, thickness of Ti diffusion barrier is 10 nm, The resistivity of the structure was 3.8 μΩ-cm at 25℃, after 400℃, 1 hour annealing, the surface of Cu thin film was degraded, and Ti barrier breakdown was found , resistivity increased sharply to 50.3 μΩ-cm.
In the multi-structure of Cu/TiNx/Si, when the temperature of annealing was brough up to 700℃, crystalline Cu3Si was found on the surface. The resistivity of Cu/TiNx/Ti/Si was found between Cu/TiNx/Si and Cu/Ti/Si, when the N2/Ar flow ratio was below 6/24 sccm, compressive stress decreased apparently, and breakdown temperature increased up to 700℃.
In the process of surface modification of Ti thin film by N2 plasma, the results showed that power effects the most to resistivity, there was 49％ η variance caused by factor of power. The time effects the most to surface roughness, there was 80％ η variance caused by factor of time.

目錄
中文摘要………………………………………………………………...…………...Ⅰ
英文摘要……………………………………………………………………..…....…Ⅱ
誌 謝……………………………………………………………………………..Ⅲ
目 錄……………………………………………………………………………..Ⅳ
圖 目 錄………………………………………………………………………….….Ⅷ
表 目 錄……………………………………………………………………..……ⅩⅢ
第一章 緒論…………………………………………………………………………..1
第二章 文獻回顧……………………………………………………………………..3
2.1 銅金屬化………………………………………………………………………3
2.1.1 IC發展趨勢……………………………………………………………3
2.1.2 導線材料之選擇…………………………………………………………4
2.1.3 銅沉積方式之比較………………………………………………………5
2.1.3.1 銅內連線之沉積方式……………………………………………….6
2.1.3.2 銅種晶層之沉積方式……………………………………………….7
2.2 阻障層之探討………………………………………………………………...9
2.2.1 阻障層機制與種類………………………………………………………9
2.2.2 阻障層材料之選擇與比較……………………………………………..10
2.2.3 阻障層之沉積方式 ……………………………………………………12
2.2.4 鈦系列阻障層之研究…………………………………………………..15
2.2.5 非鈦系列阻障層之研究………………………………………………..17
2.3低介電常數之探討…………………………………………………………..19
2.3.1 低介材沿革……………………………………………………………..19
2.3.2 低介材之需求…………………………………………………………..20
2.3.3 低介材之種類…………………………………………………………..20
2.3.4 超低介材………………………………………………………………..25
第三章 實驗步驟與分析方法………………………………………………………28
3.1 製程………………………………………………………………………….28
3.2 材料分析與量測…………………………………………………………….29
3.3 應用公式…………………………………………………………………….32
第四章 結果與討論…………………………………………………………………33
4.1 Ti與TiNx薄膜特性探討……………………………………………………33
4.1.1 AES縱深及ESCA分析………………………………………………...33
4.1.2 不同流量下之沉積速率………………………………………………..33
4.1.3片電阻（Sheet Resistance）量測……………………….………………...34
4.1.4 XRD分析………………………………………………………………..34
4.1.5 AFM表面分析……………………………………………………….…35
4.1.6 應力量測……………………………………………………………..…35
4.2. TiNx/Ti/Si結構阻障特性之探討………………………………………….....36
4.2.1片電阻（Sheet Resistance）量測…………………………………….…...36
4.2.2 應力量測………………………………………………………….…….36
4.3 Cu/Ti/Si結構阻障特性之探討…………………………………………….…37
4.3.1片電阻（Sheet Resistance）量測…………………………………………37
4.3.2 XRD分析………………………………………………………………37
4.3.3 SEM分析………………………………………………………………37
4.3.4 AFM表面分析…………………………………………………………38
4.4 Cu/TiNx/Si結構阻障特性之探討……………………………………...…….38
4.4.1片電阻（Sheet Resistance）量測…………………………………………38
4.4.2 XRD分析………………………………………………………………..38
4.4.3 SEM分析………………………………………………………………..39
4.4.4 AFM表面分析……………………………………………………….....39
4.5 Cu/TiNx/Ti/Si結構阻障特性之探討……………………………………...….40
4.5.1片電阻（Sheet Resistance）量測……………………………………...….40
4.5.2 SEM分析…………………………………………………………..……40
4.5.3應力量測…………………………………………………………..…….41
4.6 Plasma Treatment TiNx/Ti/Si結構阻障特性之探討…………………………41
4.6.1 Plasma Treatment TiNx/Ti/Si結構之ESCA…………………………….41
4.6.2片電阻（Sheet Resistance）量測…………………………………...…….42
4.6.3 XRD分析………………………………………………………………..42
4.6.4 AFM表面分析………………………………………………………….43
4.7 Cu/TiNx/HSQ/Si結構阻障特性之探討……………………………………...43
4.7.1片電阻（Sheet Resistance）量測…………………………………………43
4.7.2應力分析………………………………………………………………...44
第五章 結論…………………………………………………………………………45
參考文獻……………………………………………………………….…………….47

參考文獻
1. S. Q. Wang et al., J. of Appl. Phys., Vol. 73, No. 5, p. 2301 (1993).
2. K. Holloway et al., J. of Appl. Phys., Vol. 71, No. 11, P. 5433 (1992).
3. E. Kolawa et al., J. of Appl. Phys., Vol. 70, No. 3, p. 1369 (1991).
4. X. Sun et al., J. of Appl. Phys., Vol. 81, p. 656 (1997).
5. J. Baumann et al., Microelectronic Engineering, Vol. 37/38, p. 221 (1997).
6. H. C. Liou and J. Pretzer, Thin Solid Films, Vol. 335, p. 186 (1998).
7. D. H. Kim et al., Appl. Phys. Lett., Vol. 69, No. 27, p. 4182 (1996).
8. T. Oku et al., IEEE VLSI Multilevel Interconnect Conf. Proc., p. 182 (1995).
9. W. Wang et al., Adv. Metal and Inter. Sys. For ULSI Application, 1997.
10. K. H. Min et al., J. Vac. Sci. Technol., B, Vol. 14, p. 3263 (1996).
11. 龍文安著, “積體電路微影製程”, 高立, 台北, 民89.
12. P. Sermon, K. Beekmann and S. McClatchie, Semiconductor FABTECH, 11th edition, p. 257 (2000).
13. Andrew et al., J. Vac. Sci. Technol., B, Vol. 18(1), Jan/Feb, p. 267 (2000).
14. M. Proust et al., Microelectronic Engineering, Vol. 50, p. 369 (2000).
15. D. Popovici et al., Applied Surface Science, Vol. 126, p. 198 (1998).
16. G. Ffiese et al., Microelectronic Engineering, Vol. 37/38, p. 157 (1997).
17. K. Numajiri et al., Applied Surface Science, Vol. 100/101, p. 541 (1996).
18. T. Kodas et al., “The Chemistry of Metal CVD”, p. 253, VCH, New York, 1994.
19. J. Robert et al., Microelectronic Engineering, Vol. 37/38, p. 97 (1997).
20. C. Marcadal et al., Microelectronic Engineering, Vol. 37/38, p. 97(1997).
21. G. Herde et al., Semiconductor FABTECH, 11th Edition, p. 245 (2000).
22. R. J. Contolini et al., Solid State Technology, June, p. 155 (1997).
23. C. M. Hasennsck et al., Microelectronic Engineering, Vol. 33, p. 59 (1997).
24. B. Chin et al., Solid State Technology, July, p. 141 (1998).
25. A. Sano et al., Mat. Res. Soc. Symp. Proc., Vol. 427, p. 458 (1996).
26. M. A. Nicolt et al., Thin Solid Films, Vol. 52, p. 415 (1978).
27. M. Moussavi et al., IITC 98, IEEE, p. 295 (1998).
28. K. Abe et al., J. Vac. Sci. Technol., B, Vol. 17(4), p. 1464 (1999).
29. M. Y. Kwak et al., Thin Solid Films, Vol. 399, p. 290 (1999).
30. G. Turban et al., Microelectronic Engineering, Vol. 50, p. 509 (2000).
31. P. Motte et al., Microelectronic Engineering, Vol. 50, p. 369 (2000).
32. S. Riedel et al., Microelectronic Engineering, Vol. 55, p. 213 (2001).
33. P. Motte et al., Microelectronic Engineering, Vol. 55, p. 291 (2001).
34. S. E. Schulz et al., Microelectronic Engineering, Vol. 55, p. 45 (2001).
35. M. Fayoll et al., Microelectronic Engineering, Vol. 60, p. 119 (2002).
36. A. Alberti et al., Microelectronic Engineering, Vol. 60, p. 81 (2002).
37. S. E. Kim and C. Steinbruchel, Solid State Electronics, Vol. 43, p. 1019 (1999).
38. Q. T. Jiang et al., IEEE IITC, p. 125 (1999).
39. D. Fischer et al., Solid State Technology, Mar, p. 99 (2000).
40. D. Fischer et al., Microelectronic Engineering, Vol. 50, p. 459 (2000).
41. Y. Morand et al., Thin Solid Films, Vol. 345, p. 245 (2000).
42. G. Headt, A. Mcteer and S. Meikle, Semiconductor FABTECH, 11th edition, p. 257 (2000).
43. P. Motte et al., Microelectronic Engineering, Vol. 50, p. 487 (2000).
44. S. Bystrova, J. Holleman and P. H. Woerlee, Microelectronic Engineering, Vol. 55, p. 189 (2001).
45. Kai-Min Yin et al., Thin Solid Films, Vol. 388, p. 27 (2001).
46. Akihiko Hirata et al., J. Vac. Sci. Technol., B, Vol. 19(3), May/June, p. 788 (2001).
47. H. Wolf et al., Microelectronic Engineering, Vol. 33, p. 429 (1997).
48. I. Morey et al., Solid State Technology, June, p. 71 (1999).
49. E. Korczynski, Solid State Technology, June, p. 43 (1999).
50. K. Mikagi et al., IEDM-96, p. 365 (1996).
51. V. L. Shannon et al., Thin Solid Films, Vol. 270, p. 498 (1995).
52. P. T. Liu et al., Thin Solid Films, Vol. 332, p. 345 (1998).
53. M. J. Lobada et al., Solid State Technology, May, p. 99 (1998).
54. A. Noakes, Trikon Technical Seminar, Hsinchu, March 22rd, 2000.
55. P. Sermon et al., Semicon. Fabtech., 11th edition, p. 245 (2000).
56. R. Vrtis et al., VLSI Multilevel Interconnection Conference, p. 620 (1997).
57. S. C. sun et al., VLSI Multilevel Interconnection Conference, p. 113 (1996).
58. K. K. S. Lau et al., Proc. of Dielectrics for ULSI Multilevel Interconnect Conference, p. 11 (1999).
59. S. Lee et al., J. of Appl. Phys., Vol. 85, p. 473 (1999).
60. D. Louis et al., Microelectronic Engineering, Vol. 33, p. 429 (1997).