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研究生:張智凱
研究生(外文):Jyh-Kai Chang
論文名稱:TurboCode應用於3GPP硬體實現之研究
論文名稱(外文):Study on the implementation of Turbo Code for 3GPP
指導教授:董蘭榮董蘭榮引用關係
指導教授(外文):Lan-Rong Dung
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:83
中文關鍵詞:渦輪碼解碼器可移動視窗渦輪碼編碼器
外文關鍵詞:Turbo Decodersliding windowTurbo Encoder
相關次數:
  • 被引用被引用:6
  • 點閱點閱:516
  • 評分評分:
  • 下載下載:85
  • 收藏至我的研究室書目清單書目收藏:0
Turbo Code 提供優越的錯誤更正能力,所以被廣泛應用在無線通訊方面的應用。然而由於其龐大的運算量,大量的記憶體消耗,及複雜的運算程序,造成硬體實作上無法容易實現。基於此,本論文將討論設計Turbo Code解碼器時一些重要的設計考量,並以3GPP的Turbo Code解碼器規格,為我們實現的對象。我們將以定點方式及可移動視窗方演算法實現3GPP規格Turbo Code解碼器,並分析其對系統效能的影響。我們所提出的架構,與之前提出相關的設計做比較,將大幅減少Turbo Code解碼器的複雜度。特別在記憶體方面,大約可以解省10%~17%的儲存位元。我們提出一個低成本的3GPP規格的Turbo Code解碼器之架構,並以VLSI方式實現成晶片。最後,我們以TSMC 0.35um 1P4M COMS的製程製造這顆晶片,其操作頻率最高達50M Hz,並符合3GPP之重要規格。
Turbo Coding offers excellent capabilities of error correction and thus has been getting popular in the state-of-the-art wireless applications. However, the implementation of turbo coding requires high computing power and large memory size. How to optimize the use of computing resources and memory requirement becomes a key to design turbo coding VLSI. The thesis, therefore, addresses the critical implementation issues in terms of processing elements and memory, targeting on the turbo coding for 3GPP. Using the sliding-window algorithm, the proposed turbo coding architecture significantly reduces the implementation cost while the performance results satisfy the 3GPP specifications. Following the cell-based design flow, the thesis realizes a turbo decoder chip using TSMC 0.35mm 1P4M CMOS processes with 50MHz operation frequency. Comparing with the other reported turbo decoders, the chip saves the memory size by 10%~17% and consumes low power.
第一章:緒論
第二章:Turbo Coding的解碼架構
在本章中,對於Turbo Code的解碼架構和解碼的理論基礎有詳細的說明,同時也說明MAP演算法的相關實現理論,包含Log-MAP演算法及可移動視窗架構,此外我們也簡單介紹Turbo Code在3GPP的應用。
第三章:MAP解碼器之硬體設計考量
本章中,主要介紹MAP解碼器硬體設計之相關考量,由於Turbo Code的解碼器部份,最主要是由包含兩個軟式輸入軟式輸出解碼器。在本論文中主要探討MAP解碼器,在硬體實現時必須考慮到一些相關的參數,包含精確度分析,量化,查表及可移動視窗大小,及記憶體存取架構,對於實現Turbo Code的解碼架構系統效能的影響,透過這些參數的考量,才能夠使得我們設計出來的硬體電路更有效率,並符合系統的規格。
第四章:Turbo Coding之硬體實現
本章中,主要利用第三章所模擬出來的一些相關係數,以硬體實現Turbo Code的解碼架構,並以3GPP為我們應用的對象,介紹如何實現3GPP之Turbo Code解碼器的設計,從MAP解碼器,到交錯器都有詳細的介紹其硬體的實現方式,並利用第三章我們所提的記憶體架構,來實現Turbo Code解碼器,如此一來,記憶體所需要的儲存位元能夠減少,而且設計出來的硬體電路又能夠符合系統的規格。
第五章:結果與討論
本章中,主要介紹我們設計的硬體電路,經由Synopsys軟體合成後,分析系統的晶片效能、規格,面積及模擬驗證,最後並與目前已開發的晶片做比較,說明如何使用我們設計好的晶片。
第六章:結論與未來展望
參考文獻
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