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研究生:謝龍吉
研究生(外文):Lung-Ji Shie
論文名稱:低位元率語音編碼專用處理器
論文名稱(外文):An Application Specific Processor For Low-Bit Rate Speech Coding Processing
指導教授:林進燈林進燈引用關係
指導教授(外文):Chin-Teng Lin
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:119
中文關鍵詞:低位元率語音編碼處理器
外文關鍵詞:Low-Bit RateSpeech CodingProcessor
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語音傳輸是目前最主要也最普遍的通訊傳輸服務。在數位語音下的傳輸更有彈性,能夠降低價格、維持品質並提供保密的功能。由於使用者的增加與有限的頻寬,新的語音編碼傳輸位元率已由8Kbps(CELP)與4.8Kbps(CS-ACELP)發展至2.4Kbps(MELP)。也因為傳輸位元率的降低,語音品質就只能由更複雜的演算法來提昇,這使得實現快速語音編解碼相當困難。
本論文針對壓縮率相當高的MELP,提出一個新的語音編碼技術處理器,使用軟體─硬體雙重設計的方式使處理器的架構與指令集最佳化。處理器中使用五級的管線式架構來平衡處理速度與晶片面積,同時擁有兩個向量處理用的記憶體、四層迴圈、大範圍的記憶體資料暫存區、24 bits精確的浮點運算單元、整數運算單元、提供很大動態運算範圍8 bits的指數處理單元以及具有平行處理能力的指令。在指令長度固定為24 bits下,此處理器提供6種定址模式與三元運算。
此晶片以Cell-Based方式設計完成,使用TSMC 0.35μm製程之標準元件庫,預估能工作於60 MHz。晶片面積約為10.22㎜2。
Speech communication is the most dominant and common service in telecommunication at present. Digital transmission of speech is more elasticity, providing the opportunity of achieving cost, consistent quality, security and spectral efficiency in the systems that exploit it. Due to the increase in number of users and limited bandwidth available, the transmission rate of new digital speech coding techniques has dropped from 8Kbps(CELP), 4.8 Kbps(CS-ACELP)to 2.4Kbps(MELP). As the bit rate falling, the speech quality can only be maintained by employing very complex algorithms which are difficult to implement in fast speech coding.
This thesis investigates a new application specific processor for speech coding processing. The processor is designed to process Mixed Excitation Linear Prediction(MELP) coding which is the best and common speech compression. We use hardware-software codesign methodology to optimize the processor architecture and instruction set. The processor uses a five-stage pipeline to balance performance and core area. It has two memory banks for vector operation, four-level recurrent loops, multi-layer stacks, 24-bit floating-point unit for precision, integer unit, 8-bit exponent unit for large dynamic range operation and special instructions for parallel operation. Each instruction length is fixed as 24 bits. The processor provides six special addressing modes and 3-operand operations.
The chip is realized by using a TSMC 0.35μm 1P4M CMOS fabrication and synthesis by COMPASS cell library. The clock rate of the chip is expected to be 60 MHz and the silicon area required for the core is approximately 10.22㎜2.

中文摘要.......................................................i
英文摘要......................................................ii
誌謝.........................................................iii
目錄..........................................................iv
表目錄.......................................................vii
圖目錄......................................................viii
一ヽ緒論.......................................................1
1.1 相關研究發展現況.........................................1
1.2 研究動機.................................................2
二ヽMELP語音壓縮演算法簡介.....................................5
2.1 MELP語音壓縮演算法分析...................................5
2.1.1 編碼概述..........................................6
2.1.2 解碼概述..........................................9
2.2 MELP語音壓縮演算法實現..................................12
2.3 MELP的基本架構..........................................13
2.3.1 資料格式.........................................13
2.3.2 MELP架構分析.....................................14
三ヽ處理器架構簡介............................................18
3.1 指令集ヽ定址法..........................................18
3.1.1 定址法形式.......................................18
3.1.2 指令集...........................................22
3.2 主要架構與性能..........................................24
3.2.1 管線衝突.........................................28
3.2.2 省電設計.........................................41
3.3 晶片處理流程............................................42
四ヽ主要模組與設計架構........................................43
4.1 晶片內部各模組架構......................................43
4.1.1 程式控制.........................................43
4.1.2 控制線路.........................................43
4.1.3 資料儲存單元.....................................44
4.1.4 指標運算與迴圈控制器.............................44
4.1.5 記憶體位置運算單元...............................44
4.1.6 內ヽ外部位置匯流排控制器.........................44
4.1.7 衝突控制與運算元選擇單元.........................45
4.1.8 算數運算與邏輯運算單元...........................52
4.1.9 測試電路.........................................54
4.2 Gated Clock設計.........................................56
4.3 向量運算................................................60
4.4 浮點數格式..............................................61
4.5 晶片設計流程............................................62
五、軟體發展環境..............................................64
5.1 Assembler簡介...........................................64
5.1.1 Assembler的功能介紹..............................64
5.1.2 組合語言的發展流程...............................65
5.1.3 Assembler的執行環境與方式........................65
5.1.4 原始碼的語法程式.................................66
5.2 Emulator簡介............................................69
5.2.1 Emulator的功能介紹...............................70
5.2.2 軟體的發展流程...................................71
5.2.3 Emulator使用格式.................................72
5.2.4 Emulator主要架構.................................75
六、模擬結果與晶片設計........................................76
6.1 在32bits與24bits資料格式下的模擬結果比較................76
6.2 合成結果................................................78
6.3 佈局、封裝與Layout......................................78
6.4 RTL、Gate Level、Post-Layout模擬結果....................81
6.5 預計規格................................................84
6.6 晶片壓縮結果............................................84
6.7 與其他處理器之比較......................................85
七、結論......................................................86
參考文獻......................................................87
附錄A、MELP語音解碼處理器簡介................................A-1
管線衝突...................................................A-2
模組架構...................................................A-4
合成結果...................................................A-8
佈局、封裝及Layout.........................................A-9
RTL、Gate Level Post-Layout模擬結果.......................A-10
實測結果..................................................A-13
附錄B、指令集應用............................................B-1

參考文獻
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