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研究生:郭功耀
研究生(外文):Gang-Yaw Kuo
論文名稱:倒傳遞類神經網路之VLSI設計
論文名稱(外文):VLSI Design of Back Propagation Networks with On-Chip Learning
指導教授:張志永董蘭榮董蘭榮引用關係
指導教授(外文):Jyh-Yeong ChangLan-Rong Dung
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:78
中文關鍵詞:類神經網路超大型積體電路
外文關鍵詞:Neural NetworksVLSI
相關次數:
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  • 下載下載:242
  • 收藏至我的研究室書目清單書目收藏:2
為了使類神經網路擁有特定的能力,必須反覆學習直到每個輸入都能正確對應到所需要的輸出為止,當需要學習的資料很龐大時,學習的過程往往需要很長的一段時間。因此,許多增快學習的方法便被廣泛的討論與研究。我們若以超大型積體電路去實現類神經網路,並且使其能夠與複雜的計算機系統溝通配合,便可有效的縮短學習所消耗的時間。
在本論文中,我們利用超大型積體電路來實現倒傳遞類神經網路,這個晶片整合了學習部份以及回想部份,並且使得網路的輸入層、隱藏層以及輸出層的神經元個數能夠隨需求而任意調整。整個架構是基於單一指令多資料的精神,我們利用有限個數的運算單元去執行所需的運算,這些運算單元可由控制單元自由調度,而不僅限於某個特定的任務,最後我們以蝴蝶花分類問題以及點矩陣英文字母辨識來驗證我們的設計。

Nowadays, the industry of information appliances and communication products is growing rapidly. Intelligent products will become the key feature in the future. Artificial neural networks have the capabilities to learn and recall and are highly parallel. However, conventional computers do not support parallel computing and learning capability that are inherent in neural networks. Among the existing parallel architectures, SIMD (Single Instruction stream Multiple Data) is the most suitable for the implementation of BPN (back propagation networks). Therefore, the proposed architecture is based on SIMD. The proposed architecture uses limited number of PEs to fulfill all the operations needed for the recalling phase and the learning phase. The aim of the proposed architecture is not intended for one specific application. Therefore, the proposed BPN chip can be reconfigured to any BPN structure by modifying some parameters. Finally, two real cases are used to verify our design.

Chapter 1. Introduction …………………………………………………………. 1
1.1 Motivation …………………………………………………………………… 1
1.2 Design Flow …………………………………………………………………. 3
1.3 Thesis Outline ……………………………………………………………….. 4
Chapter 2. Back Propagation Networks ……………………………………… 6
2.1 BPN Structure ……………………………………………………………….. 6
2.2 Back-Propagation Learning Algorithm ……………………………………… 8
2.3 A Case Study ……………………………………………………………….. 11
Chapter 3. Analysis of Different Architectures ……………………………….. 17
3.1 Systolic Arrays ……………………………………………………………... 17
3.1.1 Deriving DGs from Given Algorithms …………………………… 17
3.1.2 Mapping DGs onto Array Structures ……………………………… 18
3.2 Data Flow ………………………………………………………………… 21
3.2.1 Marked Petri Net …………………………………………………… 23
3.3 SIMD ……………………………………………………………………….. 28
Chapter 4. The Proposed VLSI Architecture of BPN ………………………… 30
4.1 Specification ………………………………………………………………... 31
4.2 Control Unit ………………………………………………………………… 32
4.2.1 Scheduler …………………………………………………………… 33
4.2.2 TaskID Encoder …………………………………………………….. 34
4.2.3 Broker ………………………………………………………………. 35
4.2.4 Condition Checker ………………………………………………….. 39
4.3 Processing Element ………………………………………………………… 41
4.4 Memory Access Unit ……………………………………………………….. 49
Chapter 5. Simulation and Experiment ………………………………………... 56
5.1 Recognition of English Letters ……………………………………………... 56
5.2 Simulation ………………………………………………………………….. 59
5.3 Results Analysis ……………………………………………………………. 65
5.4 Another Example:Classification of Irises ………………………………….. 68
Chapter 6. Conclusion and Future Work ……………………………………… 71
6.1 Conclusion ………………………………………………………………….. 71
6.2 Future Work ………………………………………………………………... 74
References …………………………………………………………………………. 75

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