時脈訊號的失真和延遲在不斷變快的IC電路設計中已經變成一個非常重要的考量因素，本論文的目的是設計一個全數位控制的延遲鎖相迴路可以操作在266MHz到800MHz，並且擁有快速鎖定的能力大約十個時脈週期。這個全數位的延遲鎖相迴路採用一個全新的設計方式叫做不對稱映射尋跡，主要用於偵測相位差以及處理相位補償的功能。
本論文所提出的全數位延遲鎖相迴路使用不對稱映射尋跡設計主要由以下五個部分組成：
一、相位差產生電路：此電路用於接受迴授的時脈訊號，然後產生32階線性的相位差訊號，訊號間彼此相隔約100ps。
二、取樣電路及正緣解碼電路： 取樣電路以標準的時脈作為取樣的基準，紀錄標準的時脈和32階延遲時脈的關係，然後將此資料用於正緣解碼電路，判斷出正緣訊號出現的階數位置。
三、相位補償解碼電路：此部分承接第二部分的訊號，先經由優先權解碼電路，將最短和最適合之補償階數找出，設定最高優先權，然後將訊號送至相位補償解碼器，把相位階數轉為5bits的數位控制訊號。
四、5 bits 數位控制線性延遲電路：這個電路接收到相位補償解碼器訊號之後，會根據訊號改變輸入輸出之間的延遲路徑，進而改變時脈的延遲達到相位補償的目的
五、除頻及系統控制電路：除頻器製造出此系統的操作週期，而系統控制電路主要是相位鎖定判斷器，如果鎖定訊號確定，則除頻訊號將不會通過判斷器進而改變輸出延遲的補償值。
此篇論文所提出的方法可以成功的縮短鎖定的所需週期，而且不對稱映射尋跡可以有效的排除IC製程及其他外界因素的影響。

Clock skew is an increasing concern for high speed circuit designing. This paper describes a simple concept for realizing a fast all digital delay locked loop (ADDLL) circuit that operates at high frequency between 300Mhz and 800MHz and with fast lock time about 10 cycles. This ADDLL Circuit adopts a search method, called Asynchronous Time Mapping Tracking (ATMT), to detect and get the information of the phase error between the input and output clock and furthermore tune the output delay path for phase compensation.
The ADDLL circuits designed in the paper are consisted of five primary parts :
A. Feedback clock phase error generator : This part of the ADDLL system connected with feedback clock and generates 32 phase error outputs which has about 100ps between each other.
B. Time sampling and positive edge detector : The 32 phase error outputs feed through this part and the circuit would use the positive edge of the reference clock to sample the state of each phase error.
C. Phase error compensation decoder : After the phase error between the feedback clock and reference clock have been quantified , the decoder transfers the decimal data to 5 bits binary form used to control the delay line.
D. 5 bits digital controlled delay line : The binary data of the compensation decoder connected with the control ports of this delay line to determine how much the delay time have to been inserted between reference and feedback clock to synchronize the clock.
E. Frequency divider and system controller : The system controller is based on a phase detector(PD) has two major function, determining the data capture signal of digital delay line provided by frequency divider, and detecting the phase lock situation of the system to switch the modes of the ADDLL system.
The new methodology of the ADDLL system designing in this paper successfully shortens the locked cycles of the circuit and eliminates the affection of interconnect manufacturing variations with wire RC loading affects timing performance.
Key words：clock skew, ADDLL, ATMT.

摘要
ABSTRACT
ACKNOWLEDGEMENTS
CONTENTS
INDEX OF FIGURES
INDEX OF TABLES
CHAPTER 1 INTRODUCTION
1.1 Overview
1.2 Evaluation of existing solutions
1.3 Problem description: clock skew
1.3.1 RC wire delay model
1.3.2 Clock skew analysis
1.4 Adopted solution: All Digital Delay locked loop (ADDLL)
1.5 Objective
1.6 Organization of thesis
CHAPTER 2 THE THEORY AND NEW CONCEPT OF THE ADDLL SYSTEM
2.1 Introduction
2.2 The block diagram of the ATMT ADDLL system
2.3 Explanation of the block diagram
2.4 Asynchronous time mapping tracking (ATMT)
2.5 The model of imperfect asymmetry mapping
2.6 Remarks
CHAPTER 3 THE ARCHITECTURE OF THE ADDLL SYSTEM
3.1 Introduction
3.2 Feedback clock Phase error generator
3.3 Time sampling and positive edge detector
3.4 Phase error compensation decoder
3.5 five bits digital controlled delay line
3.6 Phase lock detector and system controller
3.7 Remarks
CHAPTER 4 THE CIRCUITS DESIGN AND SIMULATION
4.1 Introduction
4.2 Phase Error Generator
4.3 Sampling Circuits
4.4 Edge detect pre-decoder
4.5 Priority decoder
4.6 Timing Decoder
4.7 Binary weighted digital delay line
4.8 Phase detector & Frequency divider
4.9 External and internal reset controller
4.10 Remarks
CHAPTER 5 THE IMPLEMENTATION AND OPERATION OF THE SYSTEM
5.1 Introduction
5.2 Layout of the ADDLL system
5.3 Procedure of the ADDLL system
5.4 Post simulation
5.5 Post simulation at 300 MHz
5.6 Measures data analysis at 300 MHz
5.7 Post simulation at 800 MHz
5.8 Measures data analysis at 800 MHz
5.9 Lock and Re-lock at 400 MHz
5.10 Measures data analysis at 400 MHz
5.11 Remarks
CHAPTER 6 DISCUSSION AND FUTURE WORKS
6.1 Discussion
6.2 Future works
REFFERENCE

[1] Xiaohong Jiang and Susumu Horiguchi “Statistical skew modeling for general clock distribution networks in presence of process variations,” IEEE Trans. VLSI system, vol. 9, No. 5, October 2001.
[2] Harris, D.; Horowitz, M.; Liu, D. “Timing analysis with clock skew,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 18 Issue: 11 , Nov. 1999. Pages: 1608 —1618.
[3] Friedman, E.G. “Clock distribution networks in synchronous digital integrated circuits,” Proceedings of the IEEE , Volume: 89 Issue: 5 , May 2001 Pages: 665 -692
[4] Baronti, F.; Fanucci, L.; Lunardini, D.; Roncella, R.; Saletti, R., “On the differential nonlinearity of time-to-digital converters based on delay-locked-loop delay lines,” Nuclear Science, IEEE Transactions on , Volume: 48 Issue: 6 Part: 3 , Dec. 2001. Pages: 2424 -2431
[5] Guang-Kaai Dehng; Jyh-Woei Lin; Shen-Iuan Liu , “A fast-lock mixed-mode DLL using a 2-b SAR algorithm,” Solid-State Circuits, IEEE Journal of , Volume: 36 Issue: 10 , Oct. 2001. Pages: 1464 -1471
[6] Balasubramanian, K.; Rajaravivarma, V. “Delay length locked loop in target range tracking,” Southeastern Symposium on System Theory, 2001. Proceedings of the 33rd , 2001. Pages: 167 -170
[7] Akita, H.; Eto, S.; Isobe, K.; Tsuchida, K.; Toda, H.; Seki, T. “A novel analog mirror type DLL suitable for low voltage operation with self-calibration method,” ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on , 2000 . Pages: 343 -344
[8] Neil H. E. WESTE, KAMRAN ESHRAGHIAN, “Principles of CMOS VLSI Design,” Second Edition, Addison-wesley publishing company. Pages: 175-206
[9] Gopalakrishnan, P.; Odabasioglu, A.; Pileggi, L.; Raje, S. “An analysis of the wire-load model uncertainty problem,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume: 21 Issue: 1 , Jan. 2002 .Pages: 23 -31
[10] Aiqun Cao; Sirisantana, N.; Cheng-Kok Koh; Roy, K. “Synthesis of selectively clocked skewed logic circuits,” Quality Electronic Design, 2002. Proceedings. International Symposium on , 2002 . Pages: 229 —234
[11] Malavasi, E.; Zanella, S.; Min Cao; Uschersohn, J.; Misheloff, M.; Guardiani, C.
,”Impact analysis of process variability on clock skew ,“ Quality Electronic Design, 2002. Proceedings. International Symposium on , 2002 . Pages: 129 —132
[12] Harris, D.; Naffziger, S. ,”Statistical clock skew modeling with data delay variations,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 9 Issue: 6 , Dec. 2001 . pages: 888 -898
[13] Mehrotra, V.; Boning, D. “Technology scaling impact of variation on clock skew and interconnect delay,” Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International , 2001 . Pages: 122 -124