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研究生:吳承昌
研究生(外文):Chen-Chang Wu
論文名稱:藍芽系統之限制放大器及頻率調變解調器設計
論文名稱(外文):Design of Limiting Amplifier and FM Demodulator for Bluetooth System
指導教授:溫瓌岸
指導教授(外文):Kuei-Ann Wen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電資學院學程碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:68
中文關鍵詞:限制放大器頻率調變解調器
外文關鍵詞:Limiting AmplifierFM Demodulator
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限制放大器與頻率調變解調器在無線通訊前端電路中是一個非常重要的構成要素。它把通過混頻器的中頻波形放大到基頻電路所能夠處理的大小,把中頻信號轉換到基頻。增益、相位誤差度、輸入偏差電壓取消和接收訊號強度指示在設計限制放大器時是相當重要的參數。而亦會介紹到頻率升降頻解調器。在本論文中,將會介紹所採用的低中頻藍芽接收器結構。我們將會分析限制放大器的增益、相位誤差度、輸入偏差電壓取消和接收訊號強度指示以及頻率調變解調器並且加以驗證。
我們將會發展符合藍芽系統單晶片設計的射頻前端電路的設計流程,並且將會依據系統的規格來設計限制放大器與頻率調變解調器。限制放大器與頻率調變解調器所採用的製程是UMC 0.18um 1P6M製程。

Limiting amplifier and FM demodulator is an essential component in front-end circuit for wireless communications. It converts the IF signal to an appropriate voltage level from mixer and bandpass filter to the baseband DSP. Gain, phase error ,input voltage offset canceling and received signal strength indicator are the most important parameters in limiting amplifier design. In this thesis, we will present the structure of low-IF Bluetooth receiver. Analysis of the gain, phase error , input voltage offset canceling and receive signal strength indicator of the limiting amplifier and FM demodulator will be designed and analyzed .
Design flow for RF front-end had been developed to fit for digital convergence which will be described and design the limiting amplifier and FM modulator base on the Bluetooth system specifications . The limiting amplifier and FM demodulator specific is shown to fit the system specifications. The limiting amplifier and FM modulator is designed and simulated with UMC0.18um 1P6M process.

Table of Contents
摘要…………………………………………………………….i
Abstract………………………..……………………………....ii
誌謝…………………………………………..……………….iv
Table of Contents…………………………………………….v
Table Captions………....…………………………………...viii
Figure Captions………..…………………………………….ix
Chapter 1 Introduction…..…………………….....…..…1
1.1 Motivation………………………………………………1
1.2 Thesis Organization……………………………….……5
Chapter 2 Receiver Architecture………………....…...6
2.1 Introduction…………………………….……………….6
2.2 Heterodyne Receiver....……..….………….………....…6
2.3 Zero-IF Receiver………..……..….……….….…...……7
2.4 Image-Reject Receiver..….………….….....……………9
2.4.1 Hartley Architecture..….…...………...….…9
2.4.2 Weaver Architecture..…...……….…...…...10
2.5 Summary..………….……...…....……………………...10
Chapter 3 Limiting Amplifier………………………12
3.1 Introduction..….………….……...….……....…………12
3.1.1 AGC...……………………...…..…...…...……..13
3.1.2 Limiting Amplifier………….……...…...….....14
3.2 Design of Limiting Amplifier……...….………...…..16
3.2.1 Gain Stage Design…….…..…...……………...18
3.2.2 Constant Tranconductance Bias Circuit ...……22
3.2.3 Offset Canceling Circuit ……..……...…….….27
3.2.4 RSSI Circuit…….…….…...…………………..29
3.3 Simulation Results.….…….…….……...….………….31
Chapter 4 FM Demodulator.…..…….……...…..……37
4.1 Digital Demodulation.…..…….……………..…..……37
4.1.1 Binary Frequency Shift Keying.….……….….37
4.1.2 Coherent Detection of Binary FSK………..….39
4.1.3 Noncoherent Detection of Binary FSK….……39
4.2 Demodulation Approach……..………………...…..….40
4.2.1 Slope Detection……………………………..…40
4.2.2 Quadrature Detection……………………….…43
4.3 Demodulator Design………….………………...…..…45
4.4 Multiplier……………………………………...….…..48
4.4.1 Triode-Region Multiplier……………………..49
4.4.2 Sum Square Multiplier…………………....…..50
4.4.3 Gilbert-Cell Multiplier……………….….……51
4.4.4 Design of the CMOS Gilbert Cell Multiplier...53
4.4.5 Operation of CMOS Gilbert-Cell…………….54
4.4.6 Circuit and Simulation for Gilbert-Cell Multiplier
………..……………………………………….56
4.5 Other Circuit in Demodulator ……………………...…59
4.5.1 Double to Single Ended Converter……………59
4.5.2 Low Pass Filter………………………………..59
4.6 FM Demodulator Circuit and Simulation……………..62
4.7 Limiting Amplifier and FM Demodulator Circuit and Simulation …………………………………………….64
4.8 Limiting Amplifier and FM Demodulator Layout…….66
Chapter 5 Conclusions…..………………………….….67
5.1 Conclusions……………………………………...…….67
5.2 Future Work…………………………………………...67
References…….………………………….………………….68
簡歷

References
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