臺灣博碩士論文加值系統

限制放大器與頻率調變解調器在無線通訊前端電路中是一個非常重要的構成要素。它把通過混頻器的中頻波形放大到基頻電路所能夠處理的大小，把中頻信號轉換到基頻。增益、相位誤差度、輸入偏差電壓取消和接收訊號強度指示在設計限制放大器時是相當重要的參數。而亦會介紹到頻率升降頻解調器。在本論文中，將會介紹所採用的低中頻藍芽接收器結構。我們將會分析限制放大器的增益、相位誤差度、輸入偏差電壓取消和接收訊號強度指示以及頻率調變解調器並且加以驗證。
我們將會發展符合藍芽系統單晶片設計的射頻前端電路的設計流程，並且將會依據系統的規格來設計限制放大器與頻率調變解調器。限制放大器與頻率調變解調器所採用的製程是UMC 0.18um 1P6M製程。

Limiting amplifier and FM demodulator is an essential component in front-end circuit for wireless communications. It converts the IF signal to an appropriate voltage level from mixer and bandpass filter to the baseband DSP. Gain, phase error ,input voltage offset canceling and received signal strength indicator are the most important parameters in limiting amplifier design. In this thesis, we will present the structure of low-IF Bluetooth receiver. Analysis of the gain, phase error , input voltage offset canceling and receive signal strength indicator of the limiting amplifier and FM demodulator will be designed and analyzed .
Design flow for RF front-end had been developed to fit for digital convergence which will be described and design the limiting amplifier and FM modulator base on the Bluetooth system specifications . The limiting amplifier and FM demodulator specific is shown to fit the system specifications. The limiting amplifier and FM modulator is designed and simulated with UMC0.18um 1P6M process.

Table of Contents
摘要…………………………………………………………….i
Abstract………………………..……………………………....ii
誌謝…………………………………………..……………….iv
Table of Contents…………………………………………….v
Table Captions………....…………………………………...viii
Figure Captions………..…………………………………….ix
Chapter 1 Introduction…..…………………….....…..…1
1.1 Motivation………………………………………………1
1.2 Thesis Organization……………………………….……5
Chapter 2 Receiver Architecture………………....…...6
2.1 Introduction…………………………….……………….6
2.2 Heterodyne Receiver....……..….………….………....…6
2.3 Zero-IF Receiver………..……..….……….….…...……7
2.4 Image-Reject Receiver..….………….….....……………9
2.4.1 Hartley Architecture..….…...………...….…9
2.4.2 Weaver Architecture..…...……….…...…...10
2.5 Summary..………….……...…....……………………...10
Chapter 3 Limiting Amplifier………………………12
3.1 Introduction..….………….……...….……....…………12
3.1.1 AGC...……………………...…..…...…...……..13
3.1.2 Limiting Amplifier………….……...…...….....14
3.2 Design of Limiting Amplifier……...….………...…..16
3.2.1 Gain Stage Design…….…..…...……………...18
3.2.2 Constant Tranconductance Bias Circuit ...……22
3.2.3 Offset Canceling Circuit ……..……...…….….27
3.2.4 RSSI Circuit…….…….…...…………………..29
3.3 Simulation Results.….…….…….……...….………….31
Chapter 4 FM Demodulator.…..…….……...…..……37
4.1 Digital Demodulation.…..…….……………..…..……37
4.1.1 Binary Frequency Shift Keying.….……….….37
4.1.2 Coherent Detection of Binary FSK………..….39
4.1.3 Noncoherent Detection of Binary FSK….……39
4.2 Demodulation Approach……..………………...…..….40
4.2.1 Slope Detection……………………………..…40
4.2.2 Quadrature Detection……………………….…43
4.3 Demodulator Design………….………………...…..…45
4.4 Multiplier……………………………………...….…..48
4.4.1 Triode-Region Multiplier……………………..49
4.4.2 Sum Square Multiplier…………………....…..50
4.4.3 Gilbert-Cell Multiplier……………….….……51
4.4.4 Design of the CMOS Gilbert Cell Multiplier...53
4.4.5 Operation of CMOS Gilbert-Cell…………….54
4.4.6 Circuit and Simulation for Gilbert-Cell Multiplier
………..……………………………………….56
4.5 Other Circuit in Demodulator ……………………...…59
4.5.1 Double to Single Ended Converter……………59
4.5.2 Low Pass Filter………………………………..59
4.6 FM Demodulator Circuit and Simulation……………..62
4.7 Limiting Amplifier and FM Demodulator Circuit and Simulation …………………………………………….64
4.8 Limiting Amplifier and FM Demodulator Layout…….66
Chapter 5 Conclusions…..………………………….….67
5.1 Conclusions……………………………………...…….67
5.2 Future Work…………………………………………...67
References…….………………………….………………….68
簡歷

References
[1] Specification of the Bluetooth System, Dec. 1999.
[2] Theodore S. Rappaport . “Wireless Communications
Principles and Practice” 1999
[3] Jeajin park, Eurho Joe, Myung-Jun Choe, and Bang-Sup
Song, “A 5-MHz IF Digital FM Demodulator” , IEEE J. Solid-
State Circuits, vol. 34, NO. 1 ,pp. 3-11, Jan 1999
[4] Hooman Darabi, Shahla Khorram, Hung-Ming(Ed) Chien, Meng-An Pan, Stephen Wu, Sshervin Moloudi, John C. Leete, Member, IEEE, Jacob J. Rael, Student Member, IEEE, Masood Syed, Robert Lee, Brima Ibrahim, Maryam Rofougaran, and Ahmadreza Rofougaran, ”A 2.4-GHz CMOS Transceiver for Bluetooth”, IEEE J. Solid-State Circuits, vol. 36, NO. 12 ,pp. 2016-2024, Dec 2001
[5] Po-Chiun Huang, Yi-Huei Chen, and Chorng-Kuang Wang, “A 2-V 10.7-MHz CMOS Liminting Amplifier/RSSI”, IEEE J. Solid-State Circuits, vol. 35, pp. 1474-1480, Oct 2000.
[6] Po-Chiun Huang, Yi-Huei Chen, and Chorng-Kuang Wang, “A 2-V 455-kHz FM/FSK Demodulator Using Feedfordward Offset Cancellation Liminting Amplifier”, IEEE J. Solid-State Circuits, vol. 36, pp. 135-138, Jan 2001.
[7] Behzad Razavi, “Design of Analog CMOS Integrated Circuits: Chapter 4, “Differential Amplifiers”,Chaper 13,”Nonlinearity and Mismatch” , McGRAW-HILL international edition Electrical Engineering Series, 2001.
[8] Roubik gregoriant, “Introduction to CMOS OP-AMPS and COMPARATORs: Chapter 3, MOS differential amplifiers”, John Wiley & Sons, Inc. , 1999.
[9] David A. Johns , Ken Martin, , “Analog Intergrated Circuit Design : Chapter 5 Basic Opamp Design and Compensation”, John Wiley & Sons, Inc. 1997.
[10] K. Kimura, “A CMOS Logarithmic IF Amplifier with Unbalanced Source-Coupled Pairs”, IEEE Journal of Solid-State Circuits, Vol. 28. Pp.78-83, Jan 1993.
[11] H, Darabi, S. Khorram, B. Ibrahim, M. Rofougaran, A. Rofougaran,”An IF FSK Demodulator for Bluetooth in 0.35mm CMOS”, IEEE 2001 Custom Integrated Circuits Conference.
[12] Ahmadreza Rogougaran, Glenn Chang, Jacob J. Rael, James Y.-C. Chang, Maryam Rofougaran, Paul J. Chang, Masoud Djafari, Jonathan Min, Edward W. Roth, Asad A. Abidi, and Henry Samueli,”A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver in 1-mm CMOS-Part II: Receiver Design”, IEEE J. Solid-State Circuits, vol. 33, pp. 535-547, Apr 1998.
[13] LMX2240 National Semiconductor data sheet.
[14] AN-1020 National Semiconductor data sheet
[15] Behzad Razavi, “RF Microelectronics: Chapter 2, Basic Concepts in RF Design”, Prentice Hall Communication Engineering and Emerging Technology Series, 1997.
[16] J. Crols and M. S. J. Steyaert, “A 1.5GHz Highly Linear CMOS Down conversion Mixer,” IEEE Journal of Solid-State Circuits, Vol. 30,No. 7,pp.736-742, July 1995.
[17] H-J. Song and C-K Kim, “An MOS Four-Quadrant Analog Multiplier using Simple Two-Input Squaring Circuits with Source Followers,” IEEE Journal of Solid-State Circuits, Vol. 25,No.3,pp.841-848,June 1990.
[18] P. R. Gray and R. G. Meyer, Analysis and Design of ANALOG INTEGRATED CIRCUITS Third edition. John Wiely and Sons, 1993.
[19] M. R. Ahmadreza Rofougaram, James Y.-C. Chang and A. A> Abidi, “A 1GHz CMOS RF front-end IC for a direct-conversion wireless receiver,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 880-889, July 1996.
[20] J. C. Rudell, J.-J. Ou, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon, and P. R. Gray, “ A 1.9GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications”, IEEE international Solid-State Circuits Conference Digest of Technical Papers, 1997.
[21] R. Jacob Baker ,Harry W. Li and David E. Boyce,” CMOS Circuit Design, Layout, and Simulation: Chapter 26 Nonlinear Analog Circuits”, IEEE Press Series on Microelectronic Systems, 1998
[22] M. bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, pp.165-168, February 1991.
[23] Adel S. Sedra, Kenneth C. Smith,” Microelectronic Circuits third edition: Chapter 11 Filters and Tuned Amplifiers”,Saunders Collegue Publishing, 1990.
[24] Jieh-Tsorng Wu,”Analog Intergrated Circuit Class Lecture, Chapter 19:Active RC Filters”,1999.