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研究生:侯福居
研究生(外文):Fu Ju Hou
論文名稱:具鰭狀通道之蕭特基源/汲極SOI場效電晶體之製作與分析
論文名稱(外文):Fabrication and Characterization of SOI FinFETs with Schottky Barrier Source/Drain
指導教授:黃調元黃調元引用關係林鴻志林鴻志引用關係
指導教授(外文):Tiao Yuan HuangHorng Chih Lin
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電資學院學程碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:58
中文關鍵詞:鰭狀通道蕭特基
外文關鍵詞:FinFETSchottky Barrier
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在本篇論文中,我們提出並驗證了一種新結構的奈米元件,此一元件是以Fin結構為基礎而製作於SOI晶片上,更結合了以金屬矽化物形成之源/汲極和電場感應出的源/汲極延伸區為其主要特色。在元件的製作上,我們首先以電子束微影系統及選用NEB-22和HSQ兩種電子光阻來檢測奈米線寬的製作能力。HSQ電子光阻有著高對比及線寬變動性較小之特性,因此很容便可獲得50奈米以下之線寬,但其所須之劑量太高及鄰近效應問題將阻礙其實用性。因此在本實驗中選用NEB-22電子光阻配合適當的氨水處理以得到50奈米之線寬。另外在蝕刻技術上,我們使用先進的TCP蝕刻系統,發展出新的製程條件使得矽與二氧化矽的蝕刻比可達到200倍,且於蝕刻後得到相當筆直的輪廓並應用於元件的製作。
這新元件是以金屬矽化物代替高摻雜的半導體作為源/汲極之用,使得其在製程上較為簡單且製程溫度較低。然而傳統的蕭特基源/汲極元件由於金屬與半導體接面在汲極為高電場下易產生場發射(field emission)的漏電流機制,造成其具有較大之漏電流而大大地降低其開/闗之電流比,也因此扼殺了蕭特基電晶體的實用性。然而在這新元件中加上的汲極延伸(field-induced extensions)結構能完全地抑制此一漏電流機制,且元件導通電流亦隨著延伸區電壓加大而增大,完全地改善了傳統蕭特基源/汲極元件的缺點。
在元件的操作及特性上,以二矽化鈷作為源/汲極的元件在同一個元件上能藉著改變兩個閘極(main-gate and sub-gate)的電壓極性而具有兩種模式(n通道及 p通道)的操作能力,且兩種操作模式都展現了良好的特性。從量測中,我們在同一元件中得到兩種模式操作下的開/闗電流比都接近於109,且因Fin結構的作用, 亦獲得了接近物理極限的次起始斜率(subthreshold slope)值,即趨近於60mV/decade。白金矽化物(PtSi)對p通道而言有著較低之能障高(barrier height) , 因此擁有較大之導通電流,但對n通道而言卻大大地降低了導通特性。另外就傳導係數(transconductance)而言,在p通道操作模式下,白金矽化物源/汲極元件亦比二矽化鈷源/汲極元件來得高。

In this thesis, we proposed and demonstrated a novel nano-scale silicon-on-insulator (SOI) FinFET device. The new device features a metallic silicided source/drain and field-induced S/D extensions. For the device fabrication, the patterning of nano-scale Si lines using electron-beam lithography with NEB-22 or hydrogen silsesquioxane (HSQ) resist was examined firstly. Since the HSQ resist has the advantages of high contrast and less line width fluctuation up to 1nm, the sub-50nm silicon lines can be more easily achieved. Nevertheless, the required high dosage up to several hundreds µC/cm2 and the severe proximity problem make the HSQ unlikely to be used in practical applications. Therefore, NEB-22 e-beam resist, with its potentially higher commercial applicability in the future, was chosen in this work to generate sub-50nm silicon fin patterns. Concomitantly, high etch selectivity between silicon and the underlying silicon dioxide is essential to the nano-scale device fabrication, owing to the use of ultra-thin gate oxide. To overcome this issue, an advanced TCP-9400 poly-Si etcher was employed. An excellent recipe having high etching ratio (up to 200) as well as anisotropic etched profile was successfully developed in this work.
Schottky barrier (SB) MOSFETs generally enjoy simpler and low-temperature processing compared to conventional MOS transistors by employing metallic silicide, in lieu of heavily-doped region, as the source/drain. However, conventional Schottky barrier (SB) MOSFETs were known to suffer from intolerantly high leakage current caused by the field emission of carriers from the drain junction. The high leakage severely degrades the on-/off-state current ratio and essentially rules out their applications to mainstream integrated circuits. In our new device, this problem was effectively solved by the formation of an electrical drain junction which was induced by the sub-gate bias, VG,sub.
Our results show, for the first time, that the new device with Co-silicide source/drain exhibits superior ambipolar characteristics by simply switching the bias polarity on the main-gate and the sub-gate bias. Excellent subthreshold characteristics with high on-/off-state current ratio (close to or higher than 109) and near-ideal subthreshold slope (~ 60 mV/decade) are realized, for the first time, on a single device. Moreover, we show that the new device with Pt-silicided source/drain can further improve the p-channel drivability and transconductance, albeit compromising the capability of bi-channel operation, due to its low barrier height for holes (Φbop = 0.24 V) and a high barrier height for electrons (Φbon = 0.86 V).

Contents
Abstract (in Chinese) i
Abstract (in English) iii
Acknowledgement (in Chinese) v
Contents vi
Figure Captions vii
Chapter 1 Introduction 1
1.1 Backgrounds and Motivation 1
1.1.1 Advantages of FinFETs 1
1.1.2 Considerations for Source/Drain series resistance 2
1.2 SB-MOSFETs with Extremely Low Off-State Leakage
Current 2
Chapter 2 Patterning of Si Lines Using E-Beam Lithography
and High Selectivity Plasma Etching 4
2.1 E-Beam Lithography 4
2.2 Plasma Etching 5
Chapter 3 Device Fabrication, Measurements, and Operation
Principle 6
3.1 Device Fabrication 6
3.2 Device Measurements 8
3.3 Operation Principle of Schottky Barrier S/D FinFETs 10
Chapter 4 Results and Discussion 12
4.1 The Effects of Sub-Gate Bias on the Device Performance 12
4.2 Ambipolar Subthreshold Characteristics 13
4.3 Short Channel Effects 14
4.4 Output Performance 15
4.5 SB FinFETs with Pt-Silicided Source/Drain 16
Chapter 5 Conclusions 18
Reference 19

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