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研究生:蘇忠智
研究生(外文):Chung-Chih Su
論文名稱:使用於射頻收發器的一個低寄生雜頻之互補式金氧半2.4GHz頻率合成器
論文名稱(外文):The Design of a Low -Spurious -Tones CMOS Frequency Synthesizer for 2.4GHz Transceiver
指導教授:吳重雨
指導教授(外文):Prof. Chung-Yu Wu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電資學院學程碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:86
中文關鍵詞:鎖相迴路頻率合成器
外文關鍵詞:PLLfrequency synthesizer
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本論文實現了一個新型的電荷泵電路。這個電路具有完美的電流匹配特性,且可應用於2.4GHz的頻率合成電路上,用以有效地壓制雜頻的產生。實驗結果顯示本電路可使雜頻信號較主信號小七十分貝。根據其他研究指出:使用與本論文相似工作原理的電荷泵,可使雜頻信號比主信號低七十至七十五分貝。通常若使用傳統的電荷泵,雜頻信號約只比主信號小五十至六十分貝。因此本論文所提出的電路明顯地可有效壓低寄生信號的強度。
本論文中所提出的鎖相迴路式頻率合成器是以台灣積體電路零點二五微米數位類比混合式金氧半製程實現,此製程具有一層複晶矽和五層金屬。所有的電感和變容器都整合於晶片上。當使用兩伏特電源電壓時,整個晶片消耗37.4mW,晶片面積為2.56mm2。
簡而言之,本論文實現了一個低雜頻、高整合度的鎖相迴路式頻率合成器。其可應用於實現一個低成本、低消耗功率、可攜度高的無線傳收器。

This thesis implements a novel charge pump circuit with perfect current matching characteristics to be used in 2.4GHz frequency synthesizer. Conventional frequency synthesizers exhibit —50dBc ~ -60dBc spurious tones @ fref. The novel charge pump circuit that is proposed in this thesis can suppress spurious tones effectively, and can be realized easily. In this work, the measurement results exhibit the spurious tones of —70dBc @ fref below carry. There are other works with the same purpose and use different type of charge pump circuit from our approach which can achieved spurious tones of —70 ~ -75 dBc @ fref below carry as well. However, these approaches suffer clock feedthrough, and charge sharing. This PLL-based frequency synthesizers is implemented with 0.25um 1P5M mixed-mode CMOS process. All the inductors and varactors are on chip. It Consumes 37.4mW from a 2.2-V supply and occupies 2.56mm2.
In summary, this work presents a low-spurious-tones and high integration PLL-based frequency synthesizer for a low cost, low power, and high portability transceiver solutions.

ABSTRACT (CHINESE)…………………………………………….. I
ABSTRACT (ENGLISH)..……………………………………………. II
ACKNOWLEDGEMENT……………………………………………. IV
CONTENTS…………………………………………………………… V
TABLE CAPTIONS…………………………………………………... VIII
FIGURE CAPTIONS…………………………………………………. XI
CHAPTER 1 Introduction…………………………………………….. 1
1.0 Motivation……………………………………………………………….. 1
1.1 Thesis Organization……………………………………………………… 4
CHAPTER 2 Fundamentals of the PLL-Based Frequency Synthesizer. 5
2.0 Introduction……………………………………………………………… 5
2.1 Impact of Phase Noise and Spurious Tones on Frequency Synthesizer…. 6
2.2 Mathematical Model of Phase Noise and Spurious……………………… 8
2.3 s-Domain model for PLL-Based Frequency Synthesizer……………….. 14
2.3.1 Stability Analysis………………………………………………….. 14
2.3.2 Transient Analysis…………………………………………………. 18
2.4 z-Domain Model for PLL-Based Frequency Synthesizer……………….. 20
2.5 Noise Characteristic in PLL-Based Frequency Synthesizer…………….. 24
CHAPTER 3 The Design of the PLL-Base Frequency Synthesizer….. 31
3.0 Architecture of the PLL-Based Frequency Synthesizer…………………. 31
3.1 Low-Phase-Noise VCO Design…………………………………………. 32
3.2 Low-Spurious-Tones of Charge Pump Design…………………………... 38
3.2.1 Noise Sources Causing Spurious-Tones in PLL-Base frequency Synthesizer…………………………………………………… 39
3.2.2 The Strategy for Current Mismatch of Charge Pump Circuit……... 42
3.3 Design of the Frequency Divider………………………………………... 51
3.4 Phase detector design……………………………………………………. 58
3.5 Loop Filter Design and Loop Bandwidth Optimization…………………. 61
3.5.1 Design of Loop Filter………………………………………………….. 61
3.5.2 Loop Filter Optimization………………………………………………. 64
3.6 Simulation of Whole Frequency Synthesizer……………………………. 67
CHAPTER 4 Measurement Results…………………………………... 73
4.0 Spurious-Tones Measurement Results…………………………………… 74
4.1 VCO Measurement Results………………………………………………. 76
4.2 Phase Noise Measurement Results……………………………………….. 77
4.3 Summary of Measurement Results……………………………………….. 80
CHAPTER 5 Conclusions and Future Works……………………….. 82
5.0 Conclusions…………………………………………………………….. 82
5.1 Future Works…………………………………………………………….. 83
Reference………………………………………………………………. 84

[1] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, pp. 179—194, Feb. 1998.
[2] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717—724, May 1999.
[3] Jae-Shin Lee, Min-Sun Keel, Shin-II Lim and Suki Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” ELECTRONICS LETTERS, 9th, Vol.36, pp. 1907-1908, No.23 Nov 2000
[4] Lizhong Sun, Dale Nelson, “A 1.0V GHz Range 0.13μm CMOS Frequency Synthesizer,” IEEE 2001 Custom Integrated Circuits Conference, pp.327-330
[5] Thomas H. Lee, Member, IEEE, Hirad Samavati, and Hamid R. Rategh, “5-GHz CMOS Wireless LANs,” IEEE Transactions on Microwave Theory and Techniques, Vol. 50, pp. 268-280, NO. 1, Jan 2002
[6] M. V. Paemel, "Analysis of a charge-pump PLL: a new model," IEEE Trans. on Communications, vol. 42, pp. 2490-2498, July 1994.
[7] F. M. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Trans. on Communications, vol. 28, pp. 1849-1858, November 1980.
[8] Jerrel P. Hein, Jeffrey W. Scott, “Z-domain Model for Discrete-Time PLL’s,” IEEE Trans. Circuits and System , vol. 35, pp. 1393-1400, Nov 1998
[9] J. Craninckx and M. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, pp. 2054—2065, Dec. 1998.
[10] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, pp. 329—330, Feb. 1966.
[11] B. Razavi, "A study of phase noise in CMOS oscillators," IEEE J. of Solid-State Circuits, vol.31, pp. 331-343, March 1996.
[12] J. Craninckx and M. S. J. Steyaert, "A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS,” IEEE J. of Solid-State Circuits, vol.31, pp. 890-897, July 1996.
[13] Jan Craninckx and Michiel S. J. Steyaert, Wireless CMOS Frequency Synthesizer Design, Boston, MA: Kluwer Academic Publisher, 1998.
[14] Christopher Lam and Behzad Razavi, “A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-m CMOS Technology,” IEEE J. Solid-State Circuits , Vol. 35, pp. 788-794, May 2000.
[15] Joonsuk Lee and Beomsup Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control,” IEEE J. Solid-State Circuits , Vol. 35, pp. 1137-1145, Aug 2000.
[16] James F. Parker and Daniel Ray, “A 1.6-GHz CMOS PLL with On-Chip Loop Filter,” IEEE J. Solid-State Circuits, Vol. 33, pp 337-343, Mar 1998
[17] M. Johnson and E. Hudson, “A variable delay line PLL for CPU-coprocessor synchronization, ” IEEE J. Solid-State Circuits, vol. 23,pp. 1218-1223, Oct. 1988.”
[18] J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62—70, Feb. 1989.
[19] Nagendra Krishnapura and Peter R. Kinget, Member, “A 5.3-GHz Programmable Divider for HiPerLAN in 0.25-um CMOS,” IEEE J. Solid-State Circuits, Vol. 35, pp. 1019-1024, July 2000.
[20] Dan H. Wolaver, Phase-locked Loop Circuit Design, Prentice Hall, New Jersey, 1991
[21] F. M. Gardner, Phaselock Techniques, New York, NY: John Wiley & Sons, 1979.
[22] Tsung-Hsien Lin and William J. Kaiser, “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” IEEE J. Solid-State Circuits, Vol. 36, pp. 424-431, March 2001.
[23] William S. T. Yan and Howard C. Luong, “A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers,” IEEE J. Solid-State Circuits, Vol. 36, pp. 204-216, Feb. 2001.
[24] Li Lin, Luns Tee, Paul R. Gray, “A 1.4GHz Differential Low-Noise CMOS Frequency Synthesizer using a Wideband PLL Architecture,” ISSCC Digest Technical Papers, pp.
[25] Hamid R. Rategh, Hirad Samavati and Thomas H. Lee, “A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver,” IEEE J. Solid-State Circuits, Vol. 35, pp. 780-787, Feb. 2000.
[26] Chih-Ming Hung and Kenneth K. O, “A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop,” IEEE J. Solid-State Circuits, Vol. 37, pp. 521-525, April. 2002.

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