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研究生:周俊義
研究生(外文):Chou Chun-yih
論文名稱:一個高效能的雙層式查表法數位頻率合成器及其應用
論文名稱(外文):AN EFFICIENT DIRECT DIGITAL FREQUENCY SYNTHESIZER BASED ON TWO-LEVEL TABLE LOOKUP AND ITS APPLICATIONS
指導教授:陳紹基陳紹基引用關係
指導教授(外文):Chen Sau-gee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電資學院學程碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:78
中文關鍵詞:數位頻率合成器頻率合成器
外文關鍵詞:DDFSDDSTWO-LEVEL TABLE LOOKUP
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本論文提出一個新的直接數位頻率合成器(DDFS)的架構,其具備高速、 低複雜度及高頻譜純淨度。本架構主要是以正弦及餘弦泰勒展開式(Taylor’s expansion)為基礎,再結合雙層式查表演算法所構成。這個新的高效率直接數位頻率合成器,只需一個小的查表記憶體;N 位元解析度只需2N/4 組記憶體,少於其他的查表法架構,例如 Madisetti, et al. 於1999年所提出者(需2N/3 組記憶體)。依照運算方式分類,是屬於非遞迴式,因此不會產生錯誤累積的問題。本論文完成MATLAB 模擬,硬體描述語言模擬與電路合成,及FPGA 的實現;並以實際的量測結果驗證本架構在SFDR、切換速度、相位連續性及彈性Fcw範圍等項目具備良好性能。最後,以FSK 調變器來展示直接數位頻率合成器在通訊系統的應用。

This thesis proposes a new direct digital frequency synthesizer (DDFS). It has the merits of high speed, low complexity and high spectrum purity. It is based on the Taylor’s expansion method for sinusoidal and cosine functions, combined with a two-level table-lookup algorithm. The new DDFS is efficient, with a small table size and low computational complexity. In all, this new DDFS needs three lookup tables, each of size 2N/4, which is smaller than the other table-lookup methods, such as Madisetti, et al., (of size 2N/3). The DDFS is non-recursive, which is free of error-propagation problem inherently in the recursive DDFS’s.
We perform Matlab simulation, HDL simulation/synthesis and FPGA implementation to verify this algorithm. Expected SFDR, switching speed, phase continuity and flexibility Fcw were confirmed by measurements. Finally, a FSK modulator is realized to demonstrate the application of DDFS technique.

Chinese Abstract
English Abstract
Acknowledgement
Contents
List of Tables
List of Figures
Chapter 1 Introduction
1.1 Concept of frequency Synthesis
1.2 Concept of DDFS
1.3 Motivation and objective
1.4 Organization of the thesis
Chapter 2 Overview of Frequency Synthesis
2.1 Review of synthesis techniques
2.2 Existing DDFS designs
2.3 Synthesizer parameters
Chapter 3 DDFS Applications
3.1 Introduction to modulation technique of communication system
3.2 Digital modulation technique using quadrature modulator
with DDFS
Chapter 4 Principle and Architecture of Two-level Table-Lookup
DDFS
4.1 Principle of two-level table-lookup DDFS
4.2 Architecture of two-level table-lookup DDFS
4.3 Matlab simulation result
4.4 HDL simulation results
4.5 Synthesis results
4.6 Compare with existing DDFS designs
Chapter 5 FPGA Realization of New Two-level Table Lookup DDFS
5.1 Introduction of Altera FPGA 10K200SRC
5.2 Introduction of digital to analog converter
5.3 The FPGA based DDFS system
5.4 Measurement results
Chapter 6 Conclusion
References
Appendix
(1) MATLAB code of two-level table lookup DDFS
(2) Verilog code of two-level table lookup DDFS
Autobiography

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