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研究生:吳素緯
研究生(外文):Su-Wei Wu
論文名稱:在平面規劃階段的電源/接地網合成
論文名稱(外文):Fast Power/Ground Distribution Network Synthesis for Signal Integrity-Driven Floorplanning
指導教授:莊仁輝張耀文張耀文引用關係
指導教授(外文):Jen-Hui ChuangYao-Wen Chang
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電資學院學程碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:60
中文關鍵詞:電源接地合成平面規劃
外文關鍵詞:PowerGroundSynthesisFloorplanning
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在日趨複雜的電路設計中,金屬線 (metal) 長度增長,寬度減小,使電源導線的阻值增大。對於現在數位電路之趨勢是電源電壓愈來愈小,加上電源網之佈局連線的電阻值所造成的壓降,使供應元件的電壓不足,導致電路元件無法正常工作。因此,在數位電路設計中,電源 (power) 是繼時序及面積之後的重要課題。目前,大部分對電源分析的相關研究都是平坦化至基層電路元件的模型,是在完成佈局設計後再完成驗証。因此,處理上需要很高的時間及複雜度,且一旦問題發生,在設計流程也需較繁雜的反覆修正。在本論文中,我們提出一個在平坦規劃 (floorplan) 步驟中,簡單且有效的計算分析電源分佈網與理想電源的落差 (drop)。最後,我們利用商業用的佈局萃取 (layout extraction) 軟体及電源分析 (power analysis) 軟体完成驗証。驗証結果顯示,我們提出的平坦規劃階段的計算模型比較於佈局完成後元件加入電阻及寄生電容之誤差在15%。另外,我們實驗使用真實個案,在電源前題考量下完成較好的平坦規劃,驗証我們提出的計算分析模型,可以完成最佳化的平坦規劃及完成最佳化的電源分佈網,改善在設計流程上反覆修正的問題。

In deep sub-micron (DSM) technology, metal widths tend to decrease with length increasing due to the complex system integration. The resistance along the power metal line increases. Additionally, supply voltage scaling will use a lower voltage. As the result, poor power or ground levels may lead to poor logic levels, which causing incorrect operation of gates. Therefore, power is being given comparable weight to area and speed. However, most of the previous works focus on the transistor-level and post-layout verification of power distribution networks. The networks are very large, typically 1 million to 100 million nodes. Iteration cost of detecting and repairing such problems at the end of the design flow is high. In this thesis, in order to enable the single-pass design methodology, we present an efficient modeling technique for analyzing power distribution networks. The main objective is to develop a voltage drop analysis before placement. Experimental results show that the voltage drop analysis at the floorplanning stage produces no more than 15 % error compared to the post-layout voltage drop analysis. The test cases are real designs that were implemented by the Artisan 0.25um CMOS 1P5M technology. After we have applied the approach at the floorplaning stage, the voltage drop error cannot happen at the post-layout verification stage. This shows that our approach is very effective and efficient.

Chinese Abstract V
Abstract vi
Acknowledgements vii
Table of Contents viii
List of Tables x
List of Figures xi
Chapter 1. Introduction 1
1.1 Voltage Drop Effect 1
1.2 Previous Works 2
1.2.1 Power Estimation for Transistor-Based Design 3
1.2.2 Power Estimation for Cell-Based Design 4
1.2.3 Modeling the Power Network at Floorplan Stage 5
1.3 Our Contributions 6
1.4 Organization of this Thesis 7
Chapter 2. Preliminaries 8
2.1 Notation 8
2.2 Resistance Extraction 10
2.3 Macro Modeling 11
2.3.1 Soft-Macro Modeling 11
2.3.2 Hard-Macro Modeling 14
2.4 P/G Network Modeling 15
2.4.1 Single-Link Networks 15
2.4.2 Multiple-Link Networks 17
2.5 Full-Chip P/G Network Modeling 19
2.5.1 Problem Definitions 21
2.5.1.1 Voltage Drop Constraints 21
2.5.1.2 Minimum Width Constraints 21
2.5.2 P/G Network Generations 22
2.5.3 P/G Network Reductions 23
Chapter 3. Design Flow 25
3.1 Typical Design Flow 26
3.2 Proposed Design Flow 27
Chapter 4. P/G Network Analysis 29
4.1 P/G Network Algorithm 29
4.2 Analysis Algorithm 31
4.2.1 P/G Network Generation 32
4.2.2 P/G Network Computation 36
Chapter 5. Experimental Results 37
Chapter 6. Conclusions 42
Bibliography 43
Brief Biography 47

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