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研究生:王德峻
研究生(外文):Wang Der-Jiunn
論文名稱:0.25umCMOS300-1000MHz低功率低相位抖動的鎖相迴路
論文名稱(外文):A Low-Power and Low-Jitter 300-1000 MHz PLL in 0.25um CMOS Process
指導教授:李鎮宜
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電資學院學程碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:45
中文關鍵詞:鎖相迴路低相位抖動低功率工作頻率範圍廣電荷幫浦電壓控制振盪器相位頻率偵測器0.25微米互補式金氧半導體製程
外文關鍵詞:phase locked loop(PLL)low jitterlow powerwide operating frequencycharge pumpvoltage control oscillator(VCO)phase frequency detector0.25um CMOS process
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鎖相迴路可以有效地改善整個系統的時序,所以被廣泛應用在許多類比和數位積體電路輸出入介面;在這些應用中,鎖相迴路必須緊密地追隨輸入的時脈。然而,隨著對輸出入速度的要求愈來愈高,環境中的雜訊考量也愈來愈多;雜訊一般是來自電源和矽基底,常導致鎖相迴路的輸出時脈和理想時脈之間有相位抖動,所以低相位抖動在鎖相迴路的設計中變得愈來愈重要且成為必要的條件;但要達到低相位抖動卻因有許多設計的取捨考量而變得非常困難。
本論文所提出的鎖相迴路是用台灣積體電路公司0.25微米互補式金氧半導體製程設計來達到工作頻率範圍廣,低功率,特別是低相位抖動的特性。首先在此鎖相迴路運用一個對稱式回授電路在一“提靴架構”電荷幫浦,搭配一個典型的二階低通濾波器來增進相位抖動的特性。電壓控制振盪器是參考自論文研究使用差動式環型振盪器和偏壓產生器來達到較寬的工作頻率範圍和低耗電;其中的差動至單端轉換電路不僅可將差動輸入信號轉換成單端信號輸出,且此輸出即為50% 工作週期。相位頻率偵測器採用一傳統的閘邏輯電路,在同相位輸入時,可提供相等的短脈衝輸出給電荷幫浦,可防止額外的相位抖動且不影響最高工作頻率。整個鎖相迴路的模擬結果顯示工作頻率範圍從300MHz 到 1000MHz;相位抖動峰值 28.75ps,平均值 5.12ps;功率耗損小於25mW。

PLL is widely used in the I/O interfaces of many analog and digital integrated circuits in order to improve overall system timing. In these applications, PLL must closely track the input clock. However, the rising demand for high speed I/O has created an increasingly noisy environment in which PLL must function. The noise, typically in the form of supply and substrate noise, tends to cause the output clock of PLL to jitter from the ideal timing. The design of low jitter PLL has becoming important and necessary, but achieving low jitter in PLL design is difficult due to a number of design trade-offs.
The PLL is fully integrated onto TSMC 0.25um CMOS process to achieve wide operating frequency, low power and especially low jitter performance. We introduce a symmetric feedback circuit onto a “bootstrapping” charge pump with a typical second order loop filter to improve jitter performance. From thesis research, the VCO uses differential ring oscillator and bias generator to contribute wide operating frequency range and low power dissipation. The differential-to-single-ended converter can convert differential input signals into single-ended output signals with 50% duty cycle. The phase frequency detector provides equal short duration output pulses for in-phase inputs without reducing the operating frequency. The simulation results show the PLL with an operating frequency range of 300MHz to 1000MHz, peak-to-peak jitter of 28.75ps with 5.12ps RMS at 1GHz and power dissipation less than 25mW.

CHAPTER PAGE
1. Introduction 1
1-1. Thesis Motivation 1
1-2. Thesis Outline 3
2. Principles of Phase Locked Loop (PLL) 5
2-1. Basic Concept of PLL 5
2-2. Operating principles of the PLL 6
2-3. Design Specifications and Characteristic 7
2-3-1. Wide Frequency Range 8
2-3-2. Low Power 8
2-3-3. Low Jitter 9
3. Low Jitter Charge Pump 10
3-1. Basic charge pump circuit 10
3-2. Charge pump design considerations 12
3-3. Charge pump circuit improvement 14
3-4. Low jitter charge pump circuit 16
3-5 Symmetric feedback circuit 18
3-6 Charge pump comparison 20
4. PLL Circuit Design 21
4-1. Voltage Control Oscillator (VCO) 22
4-1-1. Differential ring oscillator 22
4-1-2. Wide-swing VCO bias generator 24
4-1-3. Differential-to-single converter with 50% duty
cycle output and wide swing level shift 25
4-1-4. VCO circuit block 28
4-2. Phase Frequency Detector (PFD) 29
4-3. Charge Pump (CP)& Loop Filter (LF) 32
5. Simulation Results 35
5-1 VCO Simulation Result 35
5-2 PFD Simulation Result 37
5-3 1 GHz Simulation Result 39
5-4 300 MHz Simulation Result 41
6. Conclusion 43
References 44

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