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研究生:陳玉郎
研究生(外文):Yu-Lang Chen
論文名稱:相位鎖定與延遲鎖定迴路於低成本測試機上之應用與研究
論文名稱(外文):The Study of PLL and DLL and Its Application to Low Cost Tester
指導教授:李 鎮 宜
指導教授(外文):Chen-Ye Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電資學院學程碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:48
中文關鍵詞:鎖相迴路
外文關鍵詞:PLL DLL
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測試機上之Timing Generation(TG)是測試機台上時序的控制核心,它是加速測試機台的關鍵技術。在此,我們有別於用傳統DAC、電容與比較器的方法,而改為目前較為先進的技術。利用鎖相迴路,做為4倍頻,再以一個相位延遲鎖定迴路,產生控制電壓,使倍頻鎖相迴路之輸出週期再被除4。目前我們在較低階、較少成本之技術,TSMC .6U CMOS技術模擬,可以得到 400MHZ的鎖相迴路輸出,它的週期2.5NS,被相位延遲鎖定迴路除4後為0.625NS。0.625NS為測試機最小解析度,它們足以應用於100MHZ的測試機台。以成本、對溫度的敏感性與時序調準而論,它的電路小而且有利用鎖相迴路控制時序調準,對溫度與電源的敏感性可降低。解析度較差但是準確性(accuracy)並不遜於以前之設計, RMS accuracy <3PS

A timing generator (TG) is the most important part on the tester timing control system. It is the key factor for speeding up tester's cycle rate. Here, This research uses an alternative way to build our tester timing generator. It is different from the traditional methodology, and they used to build timing generator by current steering DAC, capacitor and comparator. In this thesis, it uses a phase locked loop to multiply the input clock rate by 4, and then use a delay locked loop to divide the clock period into 4 equal sections again. The PLL and DLL simulation have been accomplished by using lower level and lower cost technology, TSMC .6U CMOS technology. Its performance could have PLL output 400MHZ clock, and the DLL output minimum stable phase delay reach 0.625ns. 0.625ns is the minimum resolution to a tester's timing generator. We could use this circuit to supply 100MHZ data rate on a tester's TG. This methodology uses extern clock to adjust PLL and DLL output. They both used the feedback loop to control their output. So the immunity to the deviation of power supply and temperature is better than the traditional design. Although its resolution is larger, its' accuracy is still better, typical RMS accuracy < 3ps.

Table of Contents
CHAPTER PAGE
1. The motivation of paper study and paper research outline 1
1-1. Embedded PLL and clock control delay line on a TG chip
2
1-2. The motivation 5
1-3. Thesis research overview 7
2. Phase locked loop study 8
2-1. Voltage control oscillator 9
2-1-1. Ring oscillator cell 9
2-1-2. VCO (Voltage Control Oscillator) bias circuit 10
2-1-3. Wide swing VCO and level shift 11
2-1-4. H-spice simulation results 12
2-2. Phase detector 14
2-3. Charge pump and loop filter 17
2-3-1. Offset-canceled charge pump operation 17
2-3-2. Charge pump and loop filter simulation 18
2-4. Truth-single-phase divider 19
2-5. 50MHZ to 500 MHZ PLL simulation 20
2-5-1. 500MHZ PLL simulation. 20
2-5-2. 500MHZ jitter calculation 22
2-5-3. 250 MHZ PLL simulation 24
2-5-4. 250MHZ PLL Jitter calculation 25
2-5-5. 50MHZ PLL simulation 26
2-6. Design review 28
3. 200HZ clock-control delay line study 29
3-1. Clock-control delay line algorithm 30
3-2. Delay cell circuit and simulation 32
3-3. Voltage control signal buffer 35
3-4. Phase detector and minimum jitter calculation 36
3-5. The minimization of locking cycle 37
3-6. Phase selector 39
3-7. Clock control delay line simulation at 200MHZ 40
3-8. Clock control delay line simulation at 125MHZ 42
3-9. Design and simulation review 44
4. Research conclusion 45
4-1. Tester timing generator specification review 45
4-2. Conclusion and feature work 47
Reference 48

References
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[4] Kau-Hsing Chen, Huan-Sen Liao, and Lin-Jiunn Tzou , “ A low jitter and low power PLL design”, ISCAS 2000 —IEEE international Symposium on circuit and system, May 28-31, 2000.
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[19] Neil H. E. West and Kamran Eshraghian, “Principles of CMOS VLSI Design A system Perspective, second edition”, Addison-Wesley 1994
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