臺灣博碩士論文加值系統

摘要
在本論文的主要目標是設計一個操作在3.3V之下、8位元、每秒150百萬次取樣(8bit,150Ms/s)的類比數位轉換器，以應用於RGB顯示器(LCD、CRT)及可攜式的儀表上。此類比數位轉換器採用平行管線化(Parallel- and-Pipelined)架構使硬體速度的需求度降低，同時可增加高速運算放大器的系統穩定時間(settling time)。此外，利用雙重取樣電路(double sampling)架構的取樣並保持電路相較傳統電路上在單位時間內有兩倍的取樣(sample)輸出。而在電路精確度的考量方面，而藉由重合一個位元的數位校正技術使得每一級(stage)的誤差容忍度有125毫伏(mV)；其中的電路之偏移誤差及所需比較器前級放大增益可藉由蒙地卡羅模擬以進行參數值估算。雙重取樣電路(double sampling)的原型晶片透過TSMC以0.25微米製程製作，面積約1.176mm×0.986mm，其量測結果與設計規格相符。而類比數位轉換器原型晶片透過TSMC以0.25微米製程製作，面積約3.136mm×2.534mm，功率消耗約467mW。

The subject of the thesis is to design an 8-bit, 150MS/s analog to digital converter(ADC) under a 3.3V supply. It can be applied in Gigabit Ethernet and RGB-to-LCD video signal processing interface circuits. This converter utilizes parallel-pipelined architecture to relax the hardware speed requirement. In addition, the Opamp can have a longer settling time under the same sampling rate. By means of double sample technique, the front end sample and hold (S/H) circuit has two times sampled data compared to traditional architectures. The coarse quantizer can tolerate 125mV comparator offset without overflow by digital error correction technique . The effect of process variation in the circuit will be estimated by Monte-Carlo simulation. The sample and hold circuit has been fabricated in TSMC 0.25μm CMOS process and occupies a chip area of 1.176mm*0.986mm. The measurement result meets our targeted specifications. The simulation result of the analog to digital converter has 0.5LSB INL and 0.6LSB DNL. The whole ADC chip is fabricated in TSMC 0.25μm CMOS process and the die size is 3.136mm*2.534mm.

摘要
目錄
圖目錄
表目錄
第一章 緒論 13
1.1 研究動機 13
1.2 論文組織 14
第二章 高速類比數位轉換器架構 15
2.1 類比數位轉換器基本原理 15
2.2 快閃式架構 18
2.3 半域轉換架構 19
2.4 雙步驟架構 20
2.5 多階管線化架構 21
2.6 時序交錯平行化架構 22
2.7 平行管線化架構 22
第三章 取樣並保持電路設計 25
3.1 取樣並保持電路基本原理 25
3.2 開迴路取樣並保持電路架構 28
3.2.1 改良型開迴路取樣並保持電路架構 31
3.2.2 開關增壓電路 31
3.3 閉迴路式取樣並保持電路 33
3.3.1 閉迴路式取樣並保持電路架構 33
3.3.2 三種基本形式的取樣並保持電路 35
3.3.3 雙重相關取樣架構之取樣保持電路 39
3.3.4 雙重取樣之取樣並保持電路 41
3.3.5 取樣並保持電路比較 42
3.3.6 取樣並保持電路設計要點 43
3.4 取樣並保持電路製作 51
3.4.1 佈局考量 51
3.4.2 動態效能模擬 51
3.4.3 電路量測 53
3.4.3 量測結果 54
3.4.4 效能總結 55
第四章 類比數位轉換系統與電路設計 57
4.1 數位校正技術 57
4.2 四階管線化架構 62
4.3 區塊電路設計 65
4.3.1 閂鎖型比較器 65
4.3.2 前置放大器 67
4.3.3 3位元量化器 69
4.3.4 編碼器 70
4.3.5 數位類比轉換器 71
4.3.6 減法器與乘法器 73
4.3.7 時序安排 75
4.4 管線化類比數位轉換器設計限制 76
4.4.1 電容匹配 76
4.4.2 電容線性度 78
4.4.3 運算放大器直流增益 79
4.4.4 運算放大器穩定時間 79
4.4.5 熱雜訊 80
4.4.6 誤差容許估計 80
4.4.7 設計限制 82
4.5 晶片製作 83
4.5.1 製程 83
4.5.2 佈局考量 83
4.5.3 量測儀表配置 85
4.5.4 性能總結 85
第五章 結論 87
參考文獻 88

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