跳到主要內容

臺灣博碩士論文加值系統

(3.239.4.127) 您好!臺灣時間:2022/08/20 07:12
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:董力中
研究生(外文):Li-Chung Tung
論文名稱:非同步AES加解密晶片之設計與實作
論文名稱(外文):Design and Implementation of an Asynchronous AES Encryption/Decryption Chip
指導教授:紀新洲
指導教授(外文):Hsin-Chou Chi
學位類別:碩士
校院名稱:國立東華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:69
中文關鍵詞:先進資料加密標準非同步微管線
外文關鍵詞:AESMicropipelineAsynchronous
相關次數:
  • 被引用被引用:3
  • 點閱點閱:268
  • 評分評分:
  • 下載下載:49
  • 收藏至我的研究室書目清單書目收藏:0
人們在網路上傳遞訊息,為了防止重要資料被有心人士所竊聽,資訊安全是很重要的一環。1977年美國國家標準局 (NBS) 公布了Data Encryption Standard (DES) 做為資料加密的標準。然而隨著計算機科學的進步,DES的安全性倍受質疑,因此NIST在2000年選定了安全性更高的Rijndael來做為未來加密的標準。Rijndael是一個反覆運算的加密演算法,它允許可變動的資料區塊及金匙的長度,分別是128 bits 、192 bits、256 bits,如果以金匙長度來看,AES的安全性高於金匙長度最大只有168 bit的Triple DES,而且AES擁有更高的加密效率。為了提供未來無線通訊的需求,低功率高效能的設計更是值得研究考量。
在本論文中,我們提出一個AES密碼器,將加密與解密功能做在同一個晶片上,增加晶片使用的自由與便利性。我們使用非同步電路架構系統來設計AES密碼器,並使用micropipeline技術,讓原本需由時脈信號控制的暫存器,改由暫存器與暫存器之間的控制訊號request及acknowledge來控制資料的傳輸。如此我們的電路完全不需要時脈的信號,免去產生clock tree的問題,也因此減少了因clock switch產生的功率消耗,達到省功率的目的。而使用管線的設計讓晶片能同時處理更多的資料,增加AES密碼器晶片的產能。
我們使用Verilog語言來設計,並使用Synopsys和Cadence等軟體實作了一個完整的密碼器晶片。整個晶片的面積為5.36 mm x 5.36 mm,throughput為1.16 Gbit/s,平均功率消耗474 mW。我們的研究顯示,此晶片的設計是可行的而且有效率。
When people transmit information over data network, hackers may attack it. Hence, the security of information is a critical issue. National Bureau of Standards (NBS) announce the Data Encryption Standard (DES) as the encryption scheme in 1977. As technology advances, the computer operates faster and faster. The DES is no longer a safe scheme security. Due to this, Rijndael is selected as the Advanced Encryption Standard (AES) in 2000 by NIST. Rijndael is a symmetric block cipher, and it allows scalable block length and the key length is 128, 192 and 256 bits. It has the properties of simplicity, high speed and proper security. To realize an AES cipher, low power and high performance are essential design issues.
This thesis presents design for the AES cipher. We combine encryption and decryption in a single chip. The design of our AES cipher uses the asynchronous architecture and micropipeline technology. There is no clock in our circuit. We use the signals request and acknowledge to control the data path instead. Since the design does not need the clock, there is no problem for generation clock tree or clock skew in a VLSI chip. Power also can be reduced since there is almost no power consumption generated by clock switch. The pipeline design allows the chip to process more data at the same time, and hence the throughput of the cipher is increased.
We have implemented the design in a VLSI chip. The chip size is 5.36 mm x 5.36 mm, and the gate count is 51 K with 36 256x8 ROM and four 16x32 RAM. The throughput is 1.16 Gbit/s and the power dissipation is 474 mW. Our results show that the design is feasible and achieves good performance.
第一章 導論......................................1
1.1 研究動機..................................1
1.2 AES的演進.................................2
1.3 非同步電路之基本概念......................3
1.3.1 非同步之通訊協定..........................3
1.3.2 非同步電路的優點..........................5
1.3.3 Micropipelines............................5
1.4 論文組織..................................9
第二章 Rijndael演算法介紹.......................10
2.1 數學背景.................................11
2.2 Rijndael演算法說明.......................12
2.2.1 Rijndael 加密演算法......................13
2.2.2 Rijndael 金匙的擴展......................18
2.2.3 Rijndael 解密演算法......................19
2.2.4 Rijndael 等價解密演算法..................22
第三章 相關研究.................................24
3.1 不同的硬體架構...........................24
3.1.1 Basic Architecture.......................24
3.1.2 Loop Unrolling...........................26
3.1.3 Inner-Round Pipelining...................26
3.1.4 Outer-Round Pipelining...................26
3.2 不同學者所提出的架構.....................26
第四章 非同步Rijndael密碼器之架構與運作方式.....33
4.1 Round Unit...............................34
4.1.1 共用區塊.................................34
4.1.2 加密區塊.................................35
4.1.3 解密區塊.................................39
4.2 Key Expansion............................41
4.3 IO Buffer................................42
4.4 Control Unit.............................44
第五章 實作與測試...............................47
5.1 實作.....................................47
5.2 模擬測試階段.............................49
5.3 比較.....................................60
第六章 結論與未來研究...........................62
參考文獻..........................................63
[1] Erik Brunvand, "Using FPGAs to Implement Self-Timed Systems," Journal of VLSI Signal Processing, 6, pp173-190, 1993, Special issue on FPGAs.

[2] Pawel Chodowiec, Kris Gaj, Peter Bellows, and Brian Schott, “Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board,” proc. Information Security Conference, Malaga, Spain, October 1-3, 2001.

[3] Andreas Dandalis, Viktor K. Prasanna, and Jose D. P. Rolim, ”A Comparative Study of Performance of AES Final Candidates Using FPGAs,” Workshop on Cryptographic Hardware and Embedded Systems, August 2000.

[4] Joan Daemen and Vincent Rijmen, “AES Proposal: Rijndael,” first AES Candidate Conference (AES1), August 20-22, 1998.

[5] Joan Daemen and Vincent Rijmen, “Answer to New Observations on Rijndael,” August 11, 2000, available at
http://www.esat.kuleuven.ac.be/~rijmen/rijndael/.

[6]A. Elbirt, W. Yip, B. Chetwynd, C.paar, “An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists,” IEEE Transactions on VLSI Systems, Vol. 9, no.4, August 2001.

[7] Kris Gaj and Pawel Chodowiec, ”Comparison of the Hardware Performance of the AES Candidates using Reconfigurable Hardware,” The Third Advanced Encryption Standard (AES3) Candidate Conference, New York, USA, April 13-14, 2000.

[8] Kris Gaj and Pawel Chodowiec, “Hardware performance of the AES finalists –survey and analysis of results,” available at
http://ece.gmu.edu/crypto/AES_survey.pdf.

[9] Tetsuya Ichikawa, Tomomi Kasuya, and Mitsuru Matsui, ”Hardware Evaluation of the AES Finalists,” AES Candidate Conference 2000: New York, New York, USA.
[10] Henry Kuo, Ingrid Verbauwhede, and Patrick Schaumont, “A 2.29 Gb/s, 56 mW Non-Pipelined Rijndael AES Encryption IC in a 1.8 V, 0.18 um CMOS Technology,” Custom Integrated Circuits Conference 2002.

[11] Ramesh Karri, Kaijie Wu, Piyush Mishra, and Yongkook Kim, ”Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture,” Defect and Fault Tolerance in VLSI Systems, 2001. Processing. 2001 IEEE International Symposium on pages(s): 427 – 435. October 24-26, 2001.

[12]Benjamin Leperchey and Charles Hymans, “FPGA Implementation of the Rijndael Algorithm,” June11, 2000, available at
http://www.di.ens.fr/~jv/HomePage/pamette/.

[13] Piotr Mroczkowski,” Implementation of the Block Cipher Rijndael Using Altera FPGA,” May 2000.

[14]Maire McLoone and John V McCanny, “Rijndael FPGA Implementation Utilizing Look-Up Tables,” Signal Processing Systems, 2001 IEEE Workshop on pages(s): 349 – 360. September 26-28, 2001.

[15] Takashi Nanya, “Asynchronous VLSI System Design,” ASP-DAC' 98 Tutorials, Yokohama, Japan February 10, 1998.

[16] National Institute of Standards and Technology, Advanced Encryption Standard (AES), Federal Information Processing Standard (FIPS) Pub 197, November 2001.

[17]Keshab K. Parhi, VLSI Digital Signal Processing Systems Design and Implementation, John Wiley & Sons Inc, 1999.

[18] RSA Security, ”RSA’s 56-bit DES Challenge,” available at http://www.rsasecurity.com/news/pr/970619-1.htm, April 2001.

[19] RSA Security, ”Team of Universities, Companies and Individual Computer Users Linked Over the Internet Crack RSA’s 56-Bit DES Challenge,” available at http://www.rsasecurity.com/news/pr/970619-1.html.

[20]William Stallings, Cryptography and Network Security: Principles and Practice Second Edition, Prentice Hall International, Inc, 1999.

[21]Ivan E. Sutherland, “Micropipelines,” Communication of the ACM, vol.22, n6, pp720734, June 1989.

[22] N. Sklavos and O. Koufopavlou, “Asynchronous Low Power VLSI Implementation of the International Data Encryption Algorithm,” Electronics, Circuits and Systems, 2001, ICECS 2001, The 8th IEEE International Conference on page(s): 1425-1428 vol.3.

[23]Patrick R. Schaumont, Henry Kuo, and Ingrid M. Verbauwhede, “Unlocking the Design Secrets of a 2.29 Gb/s Rijndael Core,” Design Automation Conference 2002.

[24] C. Sanchez-Avila and R. Sanchez-Reillo, “The Rijndael Block Cipher (AES Proposal): A Comparison with DES,” Security Technology, 2001 IEEE 35th International Carnahan Conference on page(s): 229-234. October 16-19, 2001.
.
[25]Bryan Weeks, Mark Bean, Tom Rozylowicz, Chris Ficke, ”Hardware Performance simulations of Round 2 Advanced Encryption Standard Algorithms”, available at
http://csrc.nist.gov/encryption/aes/round2/NSA-AESfinalreport.pdf.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top