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研究生:蕭志龍
研究生(外文):Chih-Lung Hsiao
論文名稱:應用於2.4GHz低電壓串疊式低雜訊放大器之設計
論文名稱(外文):The Design of Low Voltage Cascode LNAs for 2.4GHz Application
指導教授:翁若敏
指導教授(外文):Ro-Min Weng
學位類別:碩士
校院名稱:國立東華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:70
中文關鍵詞:品質因數補償低電壓低雜訊放大器
外文關鍵詞:Q-enhancementLow voltageLNA
相關次數:
  • 被引用被引用:1
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  • 下載下載:97
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在本論文中,我們嘗試兩種方法來改良串疊組態之低雜訊放大器以達到更佳之效能。第一種方法使用一個包含品質因數補償電路的差動式低雜訊放大器。我們使用一個可以產生負阻抗之主動式交叉耦合對來作為品質因數補償電路。這個補償電路可以補償負載電感之品質因數,如此可使低雜訊放大器產生較高之放大功率。較高之放大倍數可克服後級電路所產生之雜訊並可提高電路之選擇性。模擬結果顯示我們所提出之電路較傳統之架構有較高的放大功率,並且只額外增加一點點功率消耗和雜訊。
第二種方法使用一種折疊式串疊組態來降低工作電壓。將共閘極放大器折疊至另一條偏壓路徑上,工作電壓在每一條偏壓路徑上只須要偏壓一顆電晶體。使用一個電容來耦合這兩條偏壓路徑,使電路在高頻時能如同傳統串疊組態電路一般工作。較低的工作電壓也表示著較低的功率消耗,這對無線通訊設備而言是相當重要的。較低的消耗功率可延長電池之壽命,這將使手持式的設備使用起來更加便利。
採用HSPICE來模擬所提出的新型電路。第一個電路使用台灣積體電路製造公司所提供之0.35μm之製程參數。第二個電路我們使用台灣積體電路製造公司所提供之0.18μm之製程參數。所有電路主被動元件都使用高頻模型來模擬,而模擬的結果顯示這兩個電路都能符合低雜訊放大器之要求並具有極佳的特性。
In the thesis, we present two ways to improve the cascode low noise amplifier (LNA) and to achieve better performance. The first way uses a fully differential LNA with Qenhancement circuit. We use an active cross-coupled pair as a Q-compensation circuit to generate negative conductance. The Q-compensation circuit can compensate the quality
factor(Q) of the loading inductor. It makes the LNA achieve higher power gain. Higher gain can overcome the system noise and increase the sensitivity of the system. Simulation results show the proposed circuit can provide higher gain than typical structure, and just increase a little power consumption and noise.
The second way uses a folded cascode LNA to reduce the supply voltage. We folded the common gate transistor to another biasing path. The supply voltage just have to bias one transistor in each biasing path. A capacitor is used to couple the RF signal between the two biasing path and make it work like a typical cascode LNA at RF. Low supply voltage also mean lower power consumption. It is an important topic of wireless
communication circuit. Low power consumption can increase battery life. That will make handset device become more convenience.
We simulate the proposed circuits by HSPICE. The first circuit is designed by tsmc 0.35µm CMOS process. The second circuit is designed by tsmc 0.18µm CMOS process. Both circuits are simulated with RF model. And the simulation results show all the circuit can meet the specification of LNA and achieve better performance.
Abstract i
Contents ii
List of Figures iv
List of Tables vii
1 Introduction 1
1.1 Motivation . . .1
1.2 Background of LNA. . . 2
1.3 Challenges of CMOS RF IC Design . . .5
1.4 Architecture of the Thesis . . .5
2 RF IC Design Concept 7
2.1 S Parameters . . .7
2.2 Power Gain . . .9
2.3 Noise Figure . . .11
2.4 Sensitivity . . .12
2.5 Linearity . . .13
3 LNA Design 17
3.1 Noise Analysis ofMOSFET . . .17
3.1.1 Drain Noise. . . 18
3.1.2 Gate Noise. . . 19
3.1.3 MOSFET Two-Port Noise Parameters . . .21
3.1.4 Noise Optimization for Fixed Power Constrained . . .25
3.2 LNA Topology . . .28
3.2.1 Common-Gate Structure . . .28
3.2.2 Inverter Amplifier Structure . . .29
3.2.3 Common-Source Amplifier with Source Degeneration Structure . . 30
3.2.4 Cascode Structure . . .31
3.2.5 Fully Dierential Structure . . .32
3.3 On-chip Spiral Inductor and Q-enhancement Circuit . . .34
3.3.1 On-chip Spiral Inductor . . .34
3.3.2 Q-enhancement Circuit . . .36
3.4 Low Voltage Topology . . .38
4 Proposed LNA and Simulation Result 40
4.1 Proposed LNA Design . . .40
4.1.1 Fully Differential LNA with Q-enhancement Circuit . . .40
4.1.2 Low Voltage Folded Cascode LNA. . . .44
4.2 Simulation Results . . .48
4.2.1 Fully Differential LNA with Q-enhancement Circuit . . . 48
4.2.2 Low Voltage Folded Cascode LNA. . . .53
4.3 Layout Consideration . . .61
5 Conclusion 64
Bibliography 68
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