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研究生:林昆毅
研究生(外文):Kun-Yi Lin
論文名稱:應用於射頻前端發射器之1伏特AB級CMOS功率放大器
論文名稱(外文):1V Class AB CMOS Power Amplifiers for RF Front-end Transmitters
指導教授:翁若敏
指導教授(外文):Ro-Min Weng
學位類別:碩士
校院名稱:國立東華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:62
中文關鍵詞:射頻功率放大器藍芽
外文關鍵詞:Power amplifierCMOSRFTransmitterBluetooth
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由於通訊產業的蓬勃發展,使得我們對射頻積體電路的要求與日俱增例如:微細胞電話,無線電話,全球衛星定位系統,和呼叫器…等這類的可攜式個人行動通信系統,已然成為不可或缺的日常生活用品。低成本,低消耗電壓,減少外部離散元件,和高整合的積體電路,是我們電路設計者所極欲達成的目標。在以往,大多利用「砷化鎵」,或是矽基的「雙載子接面電晶體」,這種較貴的製程,來實現射頻類比前端電路,就是因為它們在高頻時有優異的性能表現,縱使如此,但很不幸的,它們這種製程卻無法與低頻部分的「金氧半場效電晶體」這種製程相容。若是射頻類比前端的電路,也利用金氧半場效電晶體來設計,那麼要將整個系統整合在一顆晶片上,就更容易了。
「功率放大器(power amplifier)」對整個通信系統的傳送端而言,扮演著一個非常重要的角色。當訊號處理完,從傳送端發送之前,我們則使用功率放大器將訊號放大,以防止訊號在傳遞過程受到干擾而失真。功率放大器所要研究的議題包含功率效率(Efficiency)、輸出功率(Output power)大小、線性度(Linearity)、阻抗匹配(Impedance matching)等,以及為了符合系統晶片(SoC)的趨勢,整合於晶片上被動元件的特性表現亦是相當重要的影響因素。本功率放大器的操作頻率為2.4GHz,直流電壓源為1V,採用tsmc 0.18μm CMOS 標準製程。
Due to the becoming development of the wireless communication, the demand of the
radio frequency (RF) IC is growing rapidly. Portable personal communication systems
such as cellar phones, cordless phones, PDA, and pagers have become a part of our daily
lives. Low cost, low power, minimizing external components and high level integration
are the objects. The analog front-end which has to operate at radio frequencies are
traditionally built form more expensive technologies like GaAs or silicon Bipolar which
are optimized to provide signal ampli cation at radio frequencies. There are several kinds
of better performance by using these two processes, but they are not compatible to the
typical CMOS process, which is used to implement the baseband circuit. If we design
the RF analog front-end circuit, it will become easier to integrate whole system into one
chip.
Power ampli er(PA) plays an important role in conventional RF front-end transmit-
ter. We utility PA to amplify transmitted signals to avoid interference and distortion
of propagation process. Thus, the performance of PA a ects the quality of wireless de-
vice. In this thesis, a folded-cascode power ampli er using tsmc CMOS 0.18 m process
is designed for 2.4GHz application. We have simulated the circuit with HSPICE, and
performed layout of PA with Cadence.The RF model of tsmc 0.18 m process is used for
the transistors and the on-chip inductors and capacitors. The supply voltage of proposed power ampli er is 1V . While RF is set to 2.4GHz, the simulation result is an output
power of 22 dBm, the maximum power-added-e ciency of 72% and a reverse transmission
coe cient of -26.8dB.
Contents
Abstract i
List of Figures v
List of Tables vii
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Review of the Transmitter Architecture . . . . . . . . . . . . . . . . . . . 2
1.3 Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 RF Circuit Design Concept 6
2.1 S-parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Re
ection Coe cient and Stability . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 Re
ection Coe cient . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 Transducer Power Gain . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.2 Available Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.3 Operating Power Gain . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 E ciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Output Power and 1-dB Compression Point . . . . . . . . . . . . . . . . 15
2.6 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Analysis of Power Ampli er 19
3.1 Classi cation of Power Ampli er . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 Class A Ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.2 Class B Ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.3 Class C Ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.4 Class AB Ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.5 Class D,E,F Ampli ers . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2 Optimal Load for Performance . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.1 Class A Power Ampli er . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.2 Class B Power Ampli er . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.3 Class E Power Ampli er . . . . . . . . . . . . . . . . . . . . . . . 37
4 Proposed Power Ampli er and Simulation Result 39
4.1 Proposed Power Ampli er . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2 Simulation Results and Layout Consideration . . . . . . . . . . . . . . . 43
4.2.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.2 Layout Consideration . . . . . . . . . . . . . . . . . . . . . . . . . 46
5 Conclusion 47
Bibliography 50
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