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研究生:曾惠亮
研究生(外文):Hui-Liang Tseng
論文名稱:數位濾波器之設計與實現
論文名稱(外文):Design and FPGA Implementation of Digital Filters
指導教授:徐忠枝魏清煌
指導教授(外文):Jong-Jy ShyuChing-Huang Wei
學位類別:碩士
校院名稱:國立高雄第一科技大學
系所名稱:電腦與通訊工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:87
中文關鍵詞:濾波器現場可規劃閘陣列濾波器組麥克連轉換
外文關鍵詞:filterFPGAfilter banksMcClellan transformation
相關次數:
  • 被引用被引用:2
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  • 下載下載:283
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  數位濾波器是數位信號處理中兩大主題之一,而現場可規劃閘陣列(FPGA)已成為ASIC設計的一種新趨勢,因此在本論文中,我們特利用FPGA來實現各種濾波器架構,包含一維濾波器、二維濾波器、全通濾波器及雙通道二維濾波器組。另外,我們亦將以麥克連轉換的技巧,以一維濾波器實現二維濾波器之架構。
  在濾波器硬體設計的過程中,係數的量化是主要的困難點所在。在本論文中,我們是以反覆拉氏乘數法求得次最佳化之量化係數,甚至我們可將係數表示成帶符號之二冪次方式,如此不需使用乘法器即可設計濾波器,降低了硬體的複雜度,也提高了執行速度。另外,我們以麥克連轉換的技術實現二維濾波器的設計,只需改變少數係數,即可改變濾波器的形狀。在架構雙通道二維濾波器組方面,我們將傳送端的分解系統與接收端的合成系統全植入同一晶片中,可用來達成編碼或解碼的動作。
  上述濾波器的實現均使用Verilog硬體描述語言與FPGA來完成,實驗驗證得到不錯的執行效率,可用於即時信號處理系統。
  Digital filters designs are one of the two main topics in digital signal processing, while FPGA has become a new trend of the ASIC design. So in this thesis we will apply FPGA technique to implement several filters including one-dimensional filters, two-dimensional filters, all-pass filters and two-channel two-dimensional filter banks. Moreover, we will realize two-dimensional filters using one-dimensional architecture by McClellan transformation.
  Coefficient quantization is the main problem while implementing the filters, and in this thesis we will use the iterative Lagrange multiplier approach to achieve sub-optimal quantized coefficients; or the coefficients can be expressed as signed-powers-of-two and the implementation can be achieved without using multipliers, which will reduce the complication of the hardware and increase the speed. In this thesis, we also implement two-dimensional filters using one-dimensional architecture by McClellan transformation techniques, and the shape of the designed filters can be changed with renewing a few coefficients. As to the implementation of two-channel two-dimensional filter banks, we combine the analysis filter banks and synthesis filter banks in a single chip, so the designed chip can be used as a coder or a decoder.
  All the above filters have been implemented by using Verilog hardware description language and FPGA technique, and the simulation shows that the performances are satisfied and the designed systems can be applied in real-time systems.
中文摘要 i
英文摘要 ii
致謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 緒 論 1
1.1 研究背景與動機 1
1.2 論文組織 2
第二章 一維濾波器設計與實現 4
2.1一維線性相位有限脈衝響應濾波器設計 4
2.1.1以權重最小均方法設計類型I低通濾波器 6
2.1.2離散係數FIR濾波器設計 8
2.2一維FIR濾波器結構 11
2.2.1濾波器係數分析與乘法器 12
2.2.2分散式算術的運用 14
2.3使用FPGA實現一維FIR濾波器 18
第三章 二維濾波器設計與實現 25
3.1二維線性相位有限脈衝響應濾波器設計 25
3.1.1設計類型I-1二維低通濾波器 25
3.1.2離散係數二維FIR濾波器設計實例 27
3.2二維FIR濾波器結構 30
3.3使用FPGA實現二維FIR濾波器 32
第四章 應用McClellan轉換的二維濾波器設計與實現 40
4.1一維濾波器至二維濾波器的轉換 40
4.2使用麥克連轉換的濾波器結構 43
4.3使用FPGA實現McClellan轉換二維濾波器 45
第五章 雙通道二維濾波器組的設計與實現 54
5.1無乘法器雙通道二維濾波器組設計 54
5.1.1設計二維完美重建濾波器 56
5.1.2設計二維離散係數濾波器 57
5.1.3設計無乘法器雙通道二維濾波器組 59
5.2雙通道二維濾波器組硬體架構 60
5.3使用FPGA實現雙通道二維濾波器組 63
第六章 全通濾波器設計與實現 70
6.1無限脈衝響應數位全通濾波器設計 70
6.2數位全通濾波器結構 72
6.3使用FPGA實現一維IIR全通濾波器 75
第七章 結 論 80
7.1結論 80
7.2未來展望 81
參考文獻 82
[1] T. W. Parks and C. S. Burrus, Digital Filter Design, John Wiley, New York, 1987, pp. 54-83.
[2] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, Prentice Hall, Inc., Englewood Cliffs, NJ, 1989.
[3] L. R. Rabiner and B. Gold, Theory and application of digital signal processing, Prentice Hall, Inc., Englewood Cliffs, 1975.
[4] L. B. Jackson, Digital filters and signal processing, Kluwer Academic Publishers, 1989.
[5] I. W. Selesnick, M. Lang, and C.S. Burrus. “Constrained Least Square Design of FIR Filters without Specified Transition Bands.” Proceedings of the IEEE Int. Conf. Acoust., Speech, Signal Processing. Vol. 2, pp. 1260-1263, May 1995.
[6] B. Friedlander and B. Porat, “The Modified Yule-Walker Method of ARMA Spectral Estimation”, IEEE Transaction on Aerospace Electronic Systems, AES-20, No. 2, pp. 158-173, March 1984.
[7] Q. Zhao and Y. Tadokoro, “A simple design of FIR filters with powers-of-two coefficients”, IEEE Trans. Circuits Syst., vol. 35, pp. 566-570, May 1988.
[8] H. Samuli, “An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients”, IEEE Trans. Circuits Syst., vol. 36, pp. 1044-1047, July 1989.
[9] Y. C. Lim and S. R. Parker, “FIR filter design over a discrete powers-of-two coefficient space”, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-31, pp. 538-591, June 1983.
[10] Y. C. Lim and S. R. Parker, “Discrete coefficient FIR digital filter design based upon an LMS criteria”, IEEE Trans. Circuits Syst., vol. CAS-30, pp. 723-739, Oct. 1983.
[11] Y. C. Lim and S. R. Parker, “Design of discrete-coefficient-value linear phase FIR filters with optimum normalized peak ripple magnitude”, IEEE Trans. Circuits Syst., vol. 37, pp. 1480-1486, Dec. 1990.
[12] H. Shaffeu, M. M. Jones, H.D. Griffiths, and J.T. Taylor, “Improved design procedure for multiplierless FIR digital filters”, Electronics Letters, vol. 27, pp. 1142-1144, June 20, 1991.
[13] N. Benvenuto, M. Marchesi, and A. Uncini, “Applications of simulated annealing for the design of special digital filters”, IEEE Trans. Signal Processing, vol. 40, pp. 323-332, Feb. 1992.
[14] R. Cemes and D. Ait-Boudaoud, “Genetic approach to design of multiplierless FIR filters”, Electronics Letters, vol. 29, pp. 2090-2091, Nov. 25, 1993.
[15] D. Ait-Boudaoud and R. Cemes, “Modified sensitivity criterion for the design of powers-of-two FIR filters”, Electronics Letters, vol. 29, pp. 1467-1469, Aug. 5, 1993.
[16] S. Powell and P. Chau, “Efficient narrowband FIR and IFIR filters based on powers-of-two sigma-delta coefficient truncation”, IEEE Trans. Circuits Syst. II, vol. 41, pp. 497-505, Aug. 1994.
[17] J. J. Shyu and Y. C. Lin, “A new approach to the design of discrete coefficient FIR digital filters”, IEEE Trans. Signal Processing, vol. 43, pp. 310-314, Jan. 1995.
[18] C. L Chen and A. N. Willson Jr., “Higher order modulation encoding for design of multiplierless FIR filters”, Electronics Letters, vol. 34, No. 24, pp. 2298-2300, Nov. 26, 1998.
[19] Y. C. Lim, R. Yang, D. Li, and J. Song, “Signed-powers-of-two term allocation scheme for the design of digital filters”, IEEE Trans. Circuits Syst. II, vol. 46, pp. 577-584, May 1999.
[20] C. L Chen and A. N. Willson Jr., “A trellis search algorithm for the design of FIR filters with signed powers-of-two coefficients”, IEEE Trans. Circuits Syst. II, vol. 46, pp. 29-39, Jan. 1999.
[21] G. Knowles, “VLSI architecture for the discrete wavelet transform,” Electronics Letters, vol. 26, no. 15, pp. 1184-1185, July 1990.
[22] M. Vishwanath, R. Owens, and M. J. Irwin, “VLSI architecture for the discrete wavelet transform,” IEEE Trans. on Circuits and Systems II, analog and digital signal processing, vol. 42, no. 5, pp. 305-316, May 1995.
[23] C. Yu, C. A. Hsieh, and S. J. Chen, “Design and implementation of a highly efficient VLSI architecture for discrete wavelet transform,” in Proc. IEEE Custom Integrated Circuits Conference, May 1997, pp. 237-240.
[24] A. S. Lewis and G. Knowles, “VLSI architecture for 2-D daubechies wavelet transform without multipliers,” Electronics Letters, vol. 27, no. 2, pp. 171-173, Jan. 1991.
[25] C. Yu and S. J. Chen, “VLSI implementation of 2-D discrete wavelet transform for real-time video signal processing,” IEEE Trans. on Consumer Electronics, vol. 43, no. 4, pp. 1270-1279, Nov. 1997.
[26] A. Peled and B. Liu, “A New Approach to the Realization of Nonrecursive Digital Filters”, IEEE Trans. Audio and Electroacoustics, vol. 21, No. 6, pp. 477-485, Dec. 1973.
[27] A. Peled and B. Liu, “A New Hardware Realization of Digital Filters”, IEEE Trans. on A.S.S.P., vol. 22, pp. 456-462, Dec. 1974.
[28] S. A. White, “Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review”, IEEE ASSP Magazine, pp. 4-19, July 1989.
[29] S. Palnitkar, Verilog HDL A Guide to Digital and Synthesis, Prentice Hall, Inc., NJ, 1996.
[30] Xilinx, “Distributed Arithmetic FIR Filter V3.0.0”, URL: www.xilinx.com/ipcenter, July 5, 2000.
[31] J. J. Shyu, Eigenfilter Approach to the Design of FIR and IIR Digital filters, Ph.D. dissertation, Electrical Engineering Department, National Taiwan University, 1992.
[32] Xilinx, Libraries Guide, Xilinx Inc., 1999.
[33] J. H. McClellan, “The design of two-dimensional digital filters by transformations”, Proc. 7th Annual Princeton Conf. Information Sciences and Systems, 1973, pp.247-251.
[34] D. E. Dudgeon and R. M. Mersereau, Multidimensional Digital Signal Processing, Prentice-Hall: Englewood Cliffs, NJ, 1984.
[35] S. C. Pei and J. J. Shyu, “Design of two-dimensional FIR digital filters by McClellan transformation and least squares eigencontour mapping”, IEEE trans. Circuits System-II, vol. 40, September 1993, pp. 546-555.
[36] E. Z. Psarakis, V. G. Mertzios, and G. P. Alexiou, “Design of two-dimensional zero phase FIR fan filters via the McClellan transform”, IEEE trans. Circuits System, vol. CAS-37, pp. 10-16, Jan. 1990.
[37] M. S. Reddy and S. N. Hazra, “Design of elliptically symmetric two-dimensional FIR filters using the McClellan transformation”, IEEE trans. Circuits System, vol. CAS-34, pp. 196-198, Feb. 1987.
[38] H. K. Kwan and C. L. Chan, “Circularly symmetric two-dimensional multiplierless FIR digital filter design using an enhanced McClellan transformation”, IEEE Proceeding, vol. 136, pp. 129-134, June 1989.
[39] D. Esteban and C. Ganlanf, “Application of quadrature mirror filters to split band voice coding cheme”, Proc. IEEE Internat. Conf. Acoust. Speech Signal Process., May 1977, pp. 191-195.
[40] B. R. Hong, H. Samueli, and A. V. Willson, “The design of low complexity linear-phase FIR filter banks using powers-of-two coefficients with an pplication to subband image coding”, IEEE Trans. Circuits Systems Video Technol., Vol. 1, December 1991, pp. 318-324.
[41] J. Woods and S. O’Neil, “Subband coding of images”, IEEE trans. Acoust. Speech Signal Process., Vol. 34, October 1986, pp. 1278-1288.
[42] J. J. Shyu, “Design of two-channel perfect-reconstruction linear-phase filter banks for subband image coding by the Lagrange multiplier approach”, IEEE Trans. Circuits Systems Video Technol., February 1995, pp. 48-51.
[43] F. J. Brophy and A. C. Salazar, “Two Design techniques for digital phase network”, Bell Syst. Tech. J., vol. 54, pp. 767-781, Apr. 1975.
[44] P. A. Bernhardt, “Simplified design of high-order recursive group-delay filters”, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-28, pp. 498-503, Oct. 1980.
[45] B. Yegnanarayana, “Design of recusive group-delay filters by autoregressive modeling”, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-30, pp. 632-637, Aug. 1982.
[46] K. P. Estola and T. Saramaki, “A new method for designing equiripple error group delay filters”, in Proc. IEEE Int. Symp. Circuits Syst., 1985, pp. 271-274.
[47] Z. Jing, “A new method for digital all-pass filter design”, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-35, pp. 1557-1564, Nov. 1987.
[48] S. C. Pei and J. J. Shyu, “Eigenfilter design of 1-D and 2-D IIR digital all-pass filters”, IEEE Trans. Signal Processing, vol. 42, pp. 996-998, Apr. 1994.
[49] B. Nobel and J. W. Daniel, Applied Linear Algebra. Englewood Cliffs, NJ: Prentice-Hall, 1977.
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