臺灣博碩士論文加值系統

近年來，影像壓縮的技術的發展成熟，應用在視訊方面的標準有MPEG 1，MPEG 2等等。本論本主要是在探討可變長度編解碼（VLC）部份，包括架構、應用及實現方法結果。
　　可變長度編解碼器的架構，分為兩種，一為串列式的架構，一為並列式的架構；本論文對這二種架構均有探討。串列式的架構，在一個工作週期只能編出或解出一個位元的碼字；而並列式的架構，能在一個工作週期，編出或解出一個碼字，而且不必考慮到該碼字的長度，所以並列式架構的可變長度編解碼器能適用於即時的系統，本論文針對此架構，模擬出該架構的工作方式，並給予硬體的實現。
　本論文的模擬方式是利用硬體描述語言Verilog，描述整個硬體工作方式，並透過Xilinx Foundation Series 3.1i模擬出波形；在實現方式是利用VLSI技術，針對並列式可變長度偵碼器，並給予硬體的實現，總晶體數為992個電晶體。

In recently, the technique of image compressing is growing up. The standard of video’s application is MPEG-1 and MPEG-2. The thesis is mainly discussing variable length codec,including the architecture, the application and the result of implementation.
The architecture of variable length codec classifies serial and parallel structures. The thesis is deeply discussing both of architectures. For serial structure, it cans encode/decode one bit of codeword in one clock. And for parallel structure, it cans encode/decode one codeword regardless of length in one clock. Therefore, the parallel structure of variable length decoder is suitable for real-time system. The parallel structure of variable length codec is simulated and implemented in this thesis.
The method of simulation is using Verilog Hardware Describe Language to describe circuit of the architecture and Xilinx Foundation Series 3.1i to simulate waveform. And the architecture is implemented the structure using VLSI technique. There are 992 transistors needed to implement the variable length detector.

目錄
中文摘要……………………………………………………………………………..Ⅰ
英文摘要……………………………………………………………………………..Ⅱ
誌謝…………………………………………………………………………………..Ⅲ
目錄…………………………………………………………………………………..Ⅳ
表目錄………………………………………………………………………………..Ⅵ
圖目錄………………………………………………………………………………Ⅶ
一、導論……………………………………………………………………………..1
1.1 研究背景…………………………………………………………………...1
1.2 研究動機…………………………………………………………………...1
　　1.3 論文架構…………………………………………………………………...2
二、視訊壓縮技術…………………………………………………………………..3
　　2.1標準化的動向……………………………………………………………….3
　　2.2影像壓縮技術的動向……………………………………………………….4
　　2.3 MPEG技術探討……………………………………………………………6
2.3.1何謂MPEG………………………………………………………………6
2.3.2 MPEG-1/2視訊壓縮方法………………………………………………...9
2.4熵(Entropy)編碼…………………………………………………………..15
2.4.1 霍夫曼編碼(Huffman Coding)…………………………………………19
三、可變長度編解碼的架構…………………………………………………………21
3.1串列式架構………………………………………………………………….21
3.1.1 串列式編碼器……………………………………………………………21
3.1.2 串列式解碼器……………………………………………………………25
3.1.2.1 直接對式架構………………………………………………………….25
3.1.2.2 管線式架構…………………………………………………………….25
3.2並列式架構………………………………………………………………….27
3.2.1並列式架構編碼器……………………………………………………….27
3.2.2並列式架構解碼器……………………………………………………….30
四、模擬結果………………………………………………………………………..32
4.1編碼器的模擬……………………………………………………………….32
4.1.1 Macroblock pattern表編碼模擬………………………………………….32
4.1.2 DCT coefficients表編碼模擬…………………………………………….35
4.2解碼器的模擬……………………………………………………………….37
4.2.1 Macroblock pattern表解碼模擬………………………………………….37
4.2.2 DCT coefficients表解碼模擬…………………………………………….40
五、硬體實現………………………………………………………………………..42
5.1 D型正反器的設計………………………………………………………….43
5.2 Barrel Shifter的設計………………………………………………………43
5.3加法器的設計……………………………………………………………….45
5.4電路的佈局(Layout)圖……………………………………………………...46
六、結論……………………………………………………………………………..51
參考資料……………………………………………………………………………..53
　　　　

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