跳到主要內容

臺灣博碩士論文加值系統

(35.168.110.128) 您好!臺灣時間:2022/08/16 06:53
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:王潔如
研究生(外文):Chieh-Ju Wang
論文名稱:實現可變長度編碼法之研究
論文名稱(外文):A Study on the Implementation of Variable Length Encoding/Decoding
指導教授:魏清煌
學位類別:碩士
校院名稱:國立高雄第一科技大學
系所名稱:電腦與通訊工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:74
中文關鍵詞:可變長度編碼法
外文關鍵詞:VLC
相關次數:
  • 被引用被引用:0
  • 點閱點閱:120
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0

本論文主要的目的是針對可變長度編解碼實現法的研究。因為近年來多媒體資訊的技術越來越進步。由於在傳輸影像的過程中對於品質的要求愈來愈高,使得影像傳輸量的需求越來越大而且速度也越來越快,所以影像壓縮的技術變得十分的重要。而所謂的資料壓縮就是在於如何拿掉多餘的資訊。而目前幾乎所有的影像壓縮標準都會採用到可變長度編碼法中的霍夫曼編碼。
在本論文中我們模擬了四種不同架構的可變長度碼的編解碼器。包括一種由Hsia和Tseng所提出的串列式架構,由Lei和Sun所提出與由Shieh、Lee和Lee所提出及我們所提出的三種並列式架構。 串列式架構所需的記憶體空間較小,但是編解碼的速度較慢。以傳統的並列式架構而言,編解碼速度較快,但由於必須將字碼的內容全部儲存於記憶體中,這樣的方法是十分浪費記憶體的空間。所以我們針對由Shieh、Lee和Lee所提出的並列式架構加以修改。將字碼的資訊加以分組處理,再利用分組都是源於同一字首的特性,使用一些簡單的數學運算,來幫助我們可以快速的找到所需的資料。
根據我們所模擬的結果顯現我們的並列式架構比傳統的並列式架構在記憶體空間的需求上是大幅度的降低,而且編解碼的速度也較Lei和Sun所提的以PLA為主的並列式架構還要快速。


The objective of this thesis is to study the implementation of variable length encoding/decoding (VLC codec). We introduce four VLC codec system architecture. First one is a bit-serial VLC codec system architecture proposed by Hsia and Tseng [1]. The others are bit-parallel VLC codec system architecture proposed by Lei and Sun [2], Shieh, Lee, and Lee [3], and us, respectively. In the bit-serial architecture, the small memory space is required to store the partial prefix bits of the codewords of the symbols, but the speed of encoding/decoding is slower. In the traditional bit-parallel architecture, the large memory space is occupied to store the codewords of the entire symbols, but the speed of encoding/decoding is faster.Our proposed bit-parallel architecture utilizes the features of the grouping codewords and symbol memory mapping and applies the numerical properties of codewords and symbol addresses to complete the overall encoding/decoding procedures. We propose an efficient group searching procedure in the encoding and decoding algorithms for our implementation. And we also introduce a symbol conversion technique to reduce the memory space required to store the codeword of the symbols. However, in our proposed architecture the encoder and the decoder can share the same table memory for storing the codeword of the symbols. In addition, the speed of encoding/decoding in our proposed bit-parallel architecture is faster than that in the PLA-based bit-parallel architecture proposed by Lei and Sun.


Abstract (in Chinese) ……………………………………………………………....i
Abstract (in English) …………………………………………………….……...….ii
Contents …………………………………………………………………………….iii
List of Abbreviations …………………………………………………….…………v
List of Figures ………………………………………………………………………vi
List of Tables ………………………………………………………………………..viii
Chapter 1 Introduction …………………………………………………………..1
1.1 Motivation ……………………………………………………………….1
1.2 Huffman Coding …………………………………………….…………..4
1.3 Thesis Organization …………………………………………………….7
Chapter 2 Variable Length Encoder and Decoder ……………………………..8
2.1 Introduction ……………………………………………………………..8
2.2 The Bit-Serial Architecture …………………………………………….9
2.2.1 The Bit-Serial Entropy Encoder ………………………………9
2.2.2 The Bit-Serial Entropy Decoder ………………………………12
2.2.2.1 The Direct-Mapped Architecture …………………...13
2.3 The Bit-Parallel Architecture …………………………………………..14
2.3.1 The Bit-Parallel Entropy Encoder ………………….…………14
2.3.2 The Bit-Parallel Entropy Decoder ………………….…………17
2.4 Our Methods ………………………………………………………...…..20
2.4.1 VLC Codec Algorithm …………………………….…………..21
2.4.1.1 Definition of Codeword Group ……………………..21
2.4.1.2 Encoding/Decoding Procedure in the Same Group..23

2.4.1.3 Group Searching Procedure ………………………..25
2.4.1.4 Overall VLC Codec Procedure ……………………..26
2.4.1.5 Memory Requirement Reduction for Symbol Information ………………………………………….30
2.4.2 VLC Codec System Architecture ……………………………...31
2.4.2.1 Group-information Detector ...……………………...33
2.4.2.2 The VLC Encoder/Decoder …………………………34
2.4.2.3 Symbol Converter and Symbol Memory …………..36
2.4.2.4 Barrel Shifter Structure …………………………….41
2.4.2.5 The Special Code Detector ………………………….43
Chapter 3 Simulation Results and Performance Comparison ………………...45
3.1 Introduction ……………………………………………………………..45
3.2 Simulation Results ……………………………………………………...45
Chapter 4 Conclusions and Future Studies …………………………………….56
4.1 Conclusions ……………………………………………………...………56
4.2 Future Studies …………………………………………………...………56
Appendix A:Corresponding Memory Address for Huffman Table 15 in MPEG2 ..58
Appendix B:Our Codeword Definition for Huffman Table 15 in MPEG2 ……62
Appendix C:Our Codeword Definition in Ascending Order for Huffman Table 15 in MPEG2 ……………………………………………….………66
Appendix D:Group Information for Huffman Table 15 in MPEG2 …………..70
References…………………………………………………………………………...72
Vita…………………………………………………………………………………..74


[1]S. C. Hsia and C. C. Tseng, ”A size-optimization design for variable length coding using distributed logic,” VLSI Design, vol. 12, no. 1, pp. 61-68, 2001.[2]S. M. Lei and M. T. Sun, “An entropy coding system for digital HDTV applications,” IEEE Trans. Circuits and Systems for Video Technology, vol. 1, no. 2, pp. 147-155, Mar. 1991.[3]B. J. Shieh, Y. S. Lee, and C. Y. Lee, “A new approach of group-based VLC codec system with full table programmability,” IEEE Trans. Circuits and Systems for Video Technology, vol. 11, no. 2. pp. 210-221, Feb. 2001. [4]K. Sayood, Introduction to Data Compression. Second Edition. San Francisco, CA: Morgan Kaufmann, 2000, pp. 39-76.[5]A. Mukherjee, N. Ranganathan, J. W. Flieder, and T. Acharya, “MARVLE: A VLSI chip for data compression using tree-based codes,” IEEE Trans. VLSI Systems, vol. 1, no. 2, pp. 203-213, June 1993.[6]S. F. Chang and D. G. Messerschmitt, “Designing a high-throughput VLC decoder PartΙConcurrent VLSI architectures,” IEEE Trans. Circuits and Systems for Video Techology, vol. 2, no. 2, pp. 187-196, June 1992.[7]H. Park and V. K. Prasanna, “Area efficient VLSI architectures for Huffman coding,” IEEE Trans. Circuits and SystemsⅡ: Analog and Digital Signal Processing, vol. 40, no. 9, pp. 568-575, Sept. 1993.[8]C. T. Hsieh and S. P. Kim, “A concurrent memory-efficient VLC decoder for MPEG applications,” IEEE Trans. Consumer Electron., vol. 42, no.3, pp. 439-446, Aug. 1996.[9]S. H. Cho, T. Xanthopoulos, and A. P. Chandrakasan, “A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning,” IEEE Trans. VLSI Systems, vol. 7, no. 2, pp. 249-257, June 1999.[10]Y. Fukuzawa, K. Hasegawa, H. Hanaki, E. Iwata, and T. Yamazali, “A programmable VLC core architecture for video compression DSP,” in Proc. IEEE SiPS’97 Design and Implementation (formerly VLSI Signal Processing), Nov. 1997, pp. 469-478.[11]K. Eshraghian, Basic VLSI Design. Third Edition, Englewood Cliffs, NJ: Prentice- Hall, 1994.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top