臺灣博碩士論文加值系統

在本篇論文中，我們提出一個低功率數位訊號處理器的實作經驗。首先，先針對其數位訊號處理器的硬體架構，以及指令集作分析與設計。之後，再加上低功率的功能，針對這一部分，提出了兩種應用方法來減少功率的消耗。在驗證上，作細部的分析，以減少測試向量的產生，如此一來，才能利用有限的人力設計和驗證數位訊號處理器。最後，以矽智產的觀念來檢視這顆數位訊號處理器。

In this thesis, we present an implementation of a low-power digital signal processor. We design the hardware units and analyze the instruction set for digital signal process applications. Besides, the power consumption issue is considered. We present two solutions to reduce the power consumption. We also discuss the test pattern generations to verify this DSP processor. Finally, the concept of IP design is considered in this design.

圖表及表格V
CHAPTER 1 導論1
1.1 研究動機1
1.2 簡介1
1.3 DSP的特點2
CHAPTER 2 相關DSP處理器3
2.1 ADI ADSP218X3
2.1.1 簡介3
2.1.2 硬體架構3
2.1.3 定址模式4
2.1.4 效能4
2.2 TI TMS320C54X5
2.2.1 簡介5
2.2.2 硬體架構5
2.2.3 定址模式6
2.2.4 效能7
2.3 比較7
CHAPTER 3 DSP相關運算9
3.1 FIR FILTER9
3.1.1 簡介9
3.1.2 數學式9
3.2 FFT9
3.2.1 簡介9
3.2.2 數學式9
3.3 數位訊號處理器上之使用11
CHAPTER 4 DSP處理器架構設計12
4.1 硬體架構介紹12
4.1.1 簡介12
4.2 管線化(PIPELINE)架構13
4.2.1 管線化的方塊圖13
4.2.2 Pre-fetch module14
4.2.3 Fetch module15
4.2.4 Decode module15
4.2.5 Access module15
4.2.6 Read module16
4.2.7 Execute/write module16
4.2.8 整體pipeline的架構17
4.3 硬體架構細節18
4.3.1 暫存器18
4.3.2 算術邏輯處理器(ALU)19
4.3.3 累加器(accumulators)20
4.3.4 移位器(barrel shifter)20
4.3.5 乘法/加法單元(multiplier/adder unit)21
4.4 定址模式22
4.4.1 定址模式簡介22
4.4.2 資料記憶體位址產生器25
CHAPTER 5 資料流的實現27
5.1 設計流程27
5.2 指令集分析28
5.2.1 指令種類28
5.2.2 實作之指令以及需要的週期28
5.2.3 實作之指令集描述29
CHAPTER 6 低功率設計33
6.1 低功率設計概論33
6.1.1 降低位元轉換次數33
6.1.2 資料流以及指令集的簡化35
6.1.3 其他35
6.2 方法一35
6.3 方法二36
6.3.1 編碼方式36
6.3.2 解碼方式36
6.3.3 額外成本36
CHAPTER 7 分析與比較37
7.1 數據37
7.1.1 Cell-based 流程37
7.1.2 FPGA38
7.2 執行週期比較38
7.2.1 FIR指令38
7.3 功率消耗比較39
7.3.1 方法一39
7.3.2 方法二40
CHAPTER 8 IP化41
8.1 IP的特性41
8.1.1 設計方面41
8.1.2 驗證方面41
8.1.3 可重複使用41
8.1.4 文件41
8.2 驗證42
8.2.1 Test pattern generation42
8.3 DSP處理器的IP 化43
參考文獻45

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