跳到主要內容

臺灣博碩士論文加值系統

(34.204.172.188) 您好!臺灣時間:2023/09/26 03:56
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:王博立
研究生(外文):Po-Li Wang
論文名稱:浮點運算CORDIC之實現與其在3D圖學之應用
論文名稱(外文):Implementation of Floating Point CORDIC and its Application in 3D Computer Graphics
指導教授:蕭勝夫
指導教授(外文):Shen-Fu Hsiao
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:74
中文關鍵詞:3D圖學浮點數座標軸數位旋轉計算器幾何轉換
外文關鍵詞:3D Computer GraphicsFloating PointCOordinate Rotation DIgital ComputerGeometric Transformation
相關次數:
  • 被引用被引用:1
  • 點閱點閱:268
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
近幾年來,電腦繪圖已成為人機介面中,最重要的資料顯示方法,並廣泛的運用在各種應用之中。例如計算機輔助設計,醫療方面的影像處理,以及電腦動畫…等等,尤其在3-D 電腦繪圖,3D engine技術的重大突破,使得這些應用可以以低成本的即時3D電腦繪圖技術為基礎。在本篇論文中,我們實作浮點運算CORDIC算術處理器,來執行許多算術運算,並利用這些數學函數的功能來輔助3D engine的設計。
Computer graphics has become one of the important method to display information and has been applied in many applications such as CAD, medical image processing, computer animation, multimedia and virtual reality. These popular applications rely on the low-cost and real-time processing of 3D graphics which become available due to the breakthrough in the hardware design of 3D graphic engine. In this thesis, we implement a CORDIC-based floating-point processor that can compute a wide variety of arithmetic operations and show how it can be applied to the design of 3D engine.
CHAPTER 1 導論1
1.1 論文架構1
1.2 研究動機1
CHAPTER 2 CORDIC相關研究3
2.1 原始的座標軸數位旋轉計算器原理:3
2.2 修正長度因子說明:4
2.3 相關研究成果6
CHAPTER 3 3D GRAPHICS之原理及硬體設計13
3.1 3-D繪圖硬體的設計目標13
3.2 標準3-D繪圖著色管線15
3.2.1 幾何轉換子系統 (Geometric Subsystem)17
3.2.2 著色子系統 (Raster Subsystem)18
3.3 克服 3-D 硬體瓶頸的技術21
3.3.1 平行化21
3.3.2 記憶體輸出入系統的改良24
CHAPTER 4 浮點運算CORDIC及其實作27
4.1 浮點運算器架構27
4.2 前置處理單元31
4.3 內部CORDIC計算器33
4.4 後置處理單元34
4.5 CORDIC FPU在MICROSPARC2上的應用35
4.6 CORDIC FPU與其他FPU的比較40
4.7 驗證與實驗數據40
4.7.1 浮點數CORDIC驗證41
4.7.2 各項實驗數據41
CHAPTER 5 幾何轉換器45
5.1 三維幾何轉換矩陣運算45
5.2 快速矩陣相乘49
5.3 矩陣相乘方向選擇器51
5.4 幾何轉換處理器59
CHAPTER 6 新的快速VECTORING CORDIC62
6.1 預測VECTORING MODE CORDIC前N/3 個ITERATIONS64
6.2 預測VECTORING MODE CORDIC後2N/3 個ITERATIONS68
CHAPTER 7 結論71
[1] J.D. Foley, A. Van Dam, S.K. Feiner, J.F. Hughes, and R.L. Phillips, Introduction to Computer Graphics. Addison-Wesley, 1994. [2] A. Watt, 3D Computer Graphics. Addison-Wesley, 2000. [3] C. C. Huang ”CORDIC-Based Sign-bit Predictable SIN-COS Generator And It’s FPGA Implementation” , 中山大學資訊工程研究所碩士論文, July 2000.[4] C. Y. Liu ”Redundant Implementation of Multi-dimensional CORDIC and their Application” , 中山大學資訊工程研究所碩士論文, July 1999.[5] J. E. Volder, "The CORDIC Trigonometric Computing Technique", IRE Trans. Electron. Comput., vol. EC-8, no. 3, Page(s): 330-334, Sept. 1959.[6] J. S. Walther, "A Unified Algorithm for Elementary Functions," Proc. Spring Joint Comput. Conf. pp. 379-385, 1971.[7] van der Kolk, K.-J.; Jeong-A Lee; Deprettere, E.F.A, “A floating point vectoring algorithm based on fast rotations”, EUROMICRO Conference, 1999. Proceedings. 25th , Volume: 1 , 1999, Page(s): 140 -147[8] Awaga, M.; Ohtsuka, T.; Yoshizawa, H.; Sasaki, S, “3D graphics processor chip”, IEEE Micro , Volume: 15 Issue: 6 , Dec. 1995, Page(s): 37 -45[9] Ide, N.; Hirano, M.; Endo, Y.; Yoshioka, S.; Murakami, H.; Kunimatsu, A.; Sato, T.; Kamei, T.; Okada, T.; Suzuoki, M. “2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing”, Solid-State Circuits, IEEE Journal of , Volume: 35 Issue: 7 , July 2000, Page(s): 1025 -1033[10] Kubosawa, H.; Higaki, N.; Ando, S.; Takahashi, H.; Asada, Y.; Anbutsu, H.; Sato, T.; Sakate, M.; Suga, A.; Kimura, M.; Miyake, H.; Okano, H.; Asato, A.; Kimura, Y.; Nakayama, H.; Kimoto, M.; Hirochi, K.; Saito, H.; Kaido, N.; Nakagawa, Y.; Shimada, T. “A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism”, Solid-State Circuits, IEEE Journal of , Volume: 34 Issue: 11 , Nov. 1999, Page(s): 1619 -1626[11] Suzuoki, M.; Kutaragi, K.; Hiroi, T.; Magoshi, H.; Okamoto, S.; Oka, M.; Ohba, A.; Yamamoto, Y.; Furuhashi, M.; Tanaka, M.; Yutaka, T.; Okada, T.; Nagamatsu, M.; Urakawa, Y.; Funyu, M.; Kunimatsu, A.; Goto, H.; Hashimoto, K.; Ide, N.; Murakami, H.; Ohtagu,”A microprocessor with a 128-bit CPU, ten floating-point MAC''s, four floating-point dividers, and an MPEG-2 decoder”, Solid-State Circuits, IEEE Journal of , Volume: 34 Issue: 11 , Nov. 1999, Page(s): 1608 -1618[12] Karagianni, K.; Paliouras, V.; Diamantakos, G.; Stouraitis, T , “Operation-saving VLSI architectures for 3D geometrical transformations”, Computers, IEEE Transactions on , Volume: 50 Issue: 6 , June 2001, Page(s): 609 -622 [13] Yoshimura, H.; Nakanishi, T.; Yamauchi, H., “A 50-MHz CMOS geometrical mapping processor”, Circuits and Systems, IEEE Transactions on , Volume: 36 Issue: 10 , Oct. 1989, Page(s): 1360 -1364[14] Karagianni, K.; Stouraitis, T. “A vector processor for 3-D geometrical transformations”, Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , Volume: 4 , 2001, Page(s): 482 -485 vol. 4[15] Acken, K.P.; Irwin, M.J.; Owens, R.M.; Garga, A.K. ”Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline”, Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on , 1996 , Page(s): 65 -71[16] Timmermann, D.; Rix, B.; Hahn, H.; Hosticka, B.J. “A CMOS floating-point vector-arithmetic unit” , Solid-State Circuits, IEEE Journal of , Volume: 29 Issue: 5 , May 1994 , Page(s): 634 -639[17]Acken, K.P.; Irwin, M.J.; Owens, R.M.; Garga, A.K. ”Architectural optimizations for a floating point multiply-accumulate unit in a graphics pipeline”, Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on , 1996 , Page(s): 65 -71[18] Kuhlmann, M.; Parhi, K.K.” A high-speed CORDIC algorithm and architecture for DSP applications ” ,Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on , 1999, Page(s): 732 -741[19] Bajard, J.-C.; Kla, S.; Muller, J.-M. “BKM: a new hardware algorithm for complex elementary functions” , Computers, IEEE Transactions on , Volume: 43 Issue: 8 , Aug. 1994, Page(s): 955 -963[20] Phatak, D.S. “Double step branching CORDIC: a new algorithm for fast sine and cosine generation” ,Computers, IEEE Transactions on , Volume: 47 Issue: 5 , May 1998, Page(s): 587 -602[21] Shaoyun Wang; Swartzlander, E.E., Jr. “Merged CORDIC algorithm” , Circuits and Systems, 1995. ISCAS ''95., 1995 IEEE International Symposium on , Volume: 3 , 1995, Page(s): 1988 -1991 vol.3[22] Wang, S.; Piuri, V.; Wartzlander, E.E., Jr. “Hybrid CORDIC algorithms”, Computers, IEEE Transactions on , Volume: 46 Issue: 11 , Nov. 1997, Page(s): 1202 -1207[23] J. D. Bruguera et. al, “Design of a pipelined radix 4 CORDIC processor“ Journal of Parallel Computing, Vol. 19, No. 7, pp. 729-244, 1993.[24] E. Antelo et. al, “High performance rotation architecture based on the radix-4 CORDIC algorithm” IEEE Trans. Computers, Vol. 46, No. 8, pp. 855-870, Aug. 1997.[25] http://www.fastgraph.com/tutorial/appendix3.html
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top