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研究生:李志峰
研究生(外文):Chih-Feng Lee
論文名稱:在叢集式伺服器上設計與實作一個以硬體為基礎的封包轉送機制
論文名稱(外文):The Design and Implementation ofHardware-based Packet Forwarding Mechanism on Web Cluster
指導教授:楊竹星楊竹星引用關係
指導教授(外文):Chu-Sing Yang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:69
中文關鍵詞:叢集式伺服器封包轉送硬體
外文關鍵詞:hardwareweb clusterforward
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近年來,由於網路快速普及化,使得網際網路(Internet)和網頁服務(web service)已經變成世界上所有主從式架構模型(Client-Server model)最廣泛的操作平台和應用,其成長之快速超出了想像空間,許多服務也逐漸由其傳統的型態轉變為以web service作為媒介。在網路負載日漸增加的情形下,伺服器的架構也就需要因應調整,其中叢集式伺服器架構最能符合擴充性、可及性與高效能的要求而備廣泛的使用。本實驗室也在之前已經完成了軟體Content-aware Distributor的設計,並將它實作在Linux的Kernel中,來有效支援content-based的遶送。
本篇論文是架構在實驗室之前的成果,由硬體設計的角度去分析,設計並實作軟體模組中能硬體化的部分,以期降低軟體負荷,加速封包處理。
我們根據對軟體模組工作分析的結果,設計與實作了硬體的封包轉送機制,切出了三個主要的功能,做成三個Engines,分別是Analyze Engine,負責過濾與分析進到Distributor的封包,決定該封包是要往上層送,或是直接轉送;Lookup Engine,負責在儲存於table的大量的連線訊息中,快速的找到該封包的資料,以供後續處理;Update Engine,以最快的時間將封包修改完成,送到另一端的send queue,我們在此Engine上利用了Patch的演算法,讓封包間與其長度無關(Packet Length Independence),使得每個封包修改的時間長度相同。
我們以Verilog HDL和Altera公司的EDA tools來完成所有的設計,並做了模擬與效能的分析,依據時序模擬結果計算Packet Forwarder處理最短封包的速度,在以時脈50MHz的速度下運作,其處理速度是兩個埠網路卡接收速度的兩倍多,因此我們可以得知這樣的子系統除了可以減少上層處理此部分工作的負擔外,並且也加速了封包轉送的工作。


The Internet and web service have become the most popularly platform and application of the Client-Server model due to the universality of the network recently years. Its growth is too fast to imagine the effect, many traditional service changes into web service stage by stage, and the load of the servers become more and more heavy. In the situation the server architecture must be adapted oppositely. The web cluster architecture has the best suit of the scalability, reliability and high performance requirement, was used extensively. We have designed and implemented a mechanism termed Content-aware Distributor, which is a software module for kernel-level extension, to effectively support content-based routing.
This paper is based on the achievement of the software-based Content-aware Distributor; we deliver some high repetition and fixity tasks to the hardware module, instead of the software module, to expect the hardware module could share the load of the software module and speedup the packet processing.
We design and implement the hardware-based packet forwarding mechanism, by the analyze result from the software module; partition three major functions into three Engines: The Analyze Engine, which is responsible to identify and analyze the header of the packet, and decide the packet needs to be send to the upper layer or forwarded; The Lookup Engine, which is responsible to lookup the address of the table which stores the data of packet modification; and the Update Engine, used to modify the packet header as soon as possible then transfer to the send queue. We use an algorithm termed Patch to fast calculate the checksums; it causes the packet length independence modification.
For the implementation, we use the Verilog HDL and EDA tools of Altera Corporation to accomplish the whole design. Simulation and evaluation the performance of processing the minimum packets, by operation at 50MHz system clock; our mechanism is faster double times than the packet receiving of two Fast Ethernet ports. From the resule we know our hardware mechanism is not only sharing the load of the upper layer, but also speedup the packet forwarding.


中文摘要……………………………………………………………………………………...1
英文摘要……………………………………………………………………………………...2
目錄...... 4
圖目錄.............................................................................................................................. 6
表目錄.............................................................................................................................. 8
一、緒論.. 9
1.1 研究動機................................................................................................................... 9
1.2 研究目標................................................................................................................. 10
1.3 研究貢獻................................................................................................................. 10
1.4 內容編排................................................................................................................. 11
二、相關研究探討................................................................................................................ 12
2.1 叢集式伺服器......................................................................................................... 12
2.2 Content-aware Distributor........................................................................................ 13
2.3 網路處理器(Network Processor) and 網路位址轉換(NAT)................................. 15
三、設計與實作.................................................................................................................... 17
3.1 設計議題................................................................................................................. 17
3.1.1 Connection Binding....................................................................................... 17
3.1.2 封包識別...................................................................................................... 18
3.1.3 Patch 演算法................................................................................................. 19
3.1.4 Mapping Table............................................................................................... 20
3.1.5 Table lookup .................................................................................................. 21
3.2 功能描述與架構..................................................................................................... 22
3.2.1 Packet Forwarder 的運作方式...................................................................... 24
3.2.2 上層介面...................................................................................................... 25
3.2.2.1 上層命令........................................................................................... 25
3.2.2.2 上層回報訊息................................................................................... 25
3.2.3 接收介面...................................................................................................... 27
3.2.4 傳送介面...................................................................................................... 27
3.3 模組設計................................................................................................................. 28
3.3.1 Analyze Engine.............................................................................................. 28
3.3.1.1 Analyze Engine 信號描述.................................................................. 29
3.1.1.2 分析資料設定................................................................................... 29
3.1.1.3 封包分析運作方式........................................................................... 30
3.3.2 Lookup Engine .............................................................................................. 32
3.3.2.1 Lookup Engine 信號描述.................................................................. 33
3.3.2.2 Mapping Table.................................................................................... 35
3.3.2.3 Lookup Table...................................................................................... 37
3.3.3 Update Engine ............................................................................................... 51
3.3.3.1 Update Engine 信號描述................................................................... 51
3.3.3.2 Update Engine 的模組....................................................................... 52
3.3.3.3 Number Adder .................................................................................... 52
3.3.3.4 Patch 模組.......................................................................................... 53
3.3.3.5 Update Engine 的運作方式............................................................... 54
3.3.4 SDRAM 控制器............................................................................................ 55
3.3.5 SDRAM Controller 驅動器.......................................................................... 55
3.4 合成......................................................................................................................... 57
3.4.1 合成工具與目的元件.................................................................................. 57
3.4.2 合成面積與工作時脈................................................................................... 57
四、模擬與驗證.................................................................................................................... 58
4.1 模擬環境設定......................................................................................................... 58
4.2 驗證方法與結果..................................................................................................... 58
4.2.1 模組功能驗證.............................................................................................. 58
4.2.2 整體驗證...................................................................................................... 60
4.2.3 時序模擬結果.............................................................................................. 61
五、效能評估........................................................................................................................ 63
六、結論與未來展望............................................................................................................ 65
七、參考文獻........................................................................................................................ 67


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