臺灣博碩士論文加值系統

這篇論文提出了三個適用於低電壓動態隨機存取記憶體 (DRAM) 之高速度電路。 首先，一個具有高驅動力的電壓提帶式字組線驅動器被提出。 它是以一個NMOS 搭配高效率的升壓電路以取代PMOS來做為拉上元件，藉此增加輸出級的電流驅動力。 當驅動相當於512個儲存格之負載與在1.5V供應電壓的情況下，所提出的字組線驅動器之切換時間比傳統的字組線驅動器快1.13ns，字組線的切換速度被改善了31.1%。 第二，一個以脈波控制過驅動時間的感應放大器 (PCO-SA) 被提出。 吾人能夠利用脈波產生器所產生的脈波來控制感應電晶體的過驅動時間，以此來暫態的增大感應電晶體的閘源極電壓並改善感應速度。 在1.5伏的供應電壓下，PCO-SA 的感應速度比傳統的感應放大器快4.4ns，感應時間被改善了34.1%。 此外，即使供應電壓被減少至1.3伏，PCO-SA仍能正常工作，但傳統的感應放大器無法在此情況下正常工作。 第三，一個修改的 N&PMOS交錯耦合型主放大器被提出。 這個修改的主放大器之構想是使加速電路具有傳送完整供應電壓給第二級之輸入的能力。 利用這種方法，修改的主放大器之資料讀出速度比傳統的快5.87ns，資料的讀出時間被改善了30.4%。 最後，此篇論文所提出之三個高速電路被整合在1-Kbit動態隨機存取記憶體測試電路之中供驗證。 當此測試電路在1.5V供應電壓時，由模擬的結果得知RAS存取時間為28.9ns，整體的RAS 存取時間被改善了16%。 這亦表示此三個電路技術可被應用於低供應電壓之動態隨機存取記憶體電路中。

Three high speed circuit schemes for a low supply voltage DRAM are presented in this thesis. First, a high drivability bootstrapped word line driver is proposed. We use one boosting circuit collocating an NMOS to serve as the pulling up device rather than a PMOS to increase the current driving ability of the output stage. When the driving loading is 512 memory cells with the supply voltage of 1.5V, the switching time of the proposed word line driver is 1.13ns faster than that of the conventional one, the switching speed of the word line is 31.1% improved. Second, a pulse-controlled overdriven sense amplifier (PCO-SA) is proposed. We can make use of the pulse width of a pulse generator to control the overdriven time of the sensing transistors thereby enlarging the VGS of the sensing transistors transiently and improving the sensing speed. The sensing speed of the PCO-SA is 4.4ns faster than that of conventional sense amplifier with the supply voltage of 1.5V, the sensing time is 34.1% improved. In addition, even if the supply voltage is decreased to 1.3V, the function of the PCO-SA still correctly, whereas conventional sense amplifier cannot. Third, a modified N&PMOS cross-coupled main amplifier is presented. We make the charging path of speedy circuit which has the ability of passing the full VDD voltage to the input of the second stage. By this way, the data read out speed of the modified main amplifier is 5.87ns faster than that of the conventional N&PMOS cross-coupled main amplifier, the data read out time is 30.4% improved. Finally, three proposed circuits in this thesis are integrated and examined in a 1-Kbit DRAM test circuit. The simulated RAS access time of 28.9ns is achieved with the supply voltage of 1.5V, the RAS access time is 16% improved. These also indicate that the proposed circuit schemes are suitable for application in a low supply voltage DRAM.

Chapter 1 Introduction.............................1
Chapter 2 The Basic Architecture of the DRAM.................................6
2.1 Basic Architecture and Operation of a DRAM......... .........7
2.2 Critical Parts of Sensing Path of a DRAM.....................7
Chapter 3 The Modified Word Lind Driver.....................................21
3.1 The Full Swing Bootstrapped CMOS Driver.....................22
3.2 The Bootstrapped Inverter...................................24
3.3 The Modified Word Line Driver...............................25
3.4 Summary.....................................................26
Chapter 4 The High Speed Sense Amplifier....................................39
4.1 The Modified Sense Amplifier................................40
4.2 The Modified Main Amplifier.................................42
4.3 Summary.....................................................45
Chapter 5 Simulated Results of the DRAM with High Speed Circuits Proposed...63
Chapter 6 Conclusion........................................................70
Reference...................................................................72
Appendix....................................................................76

[1] Mikio Asakura and Kazutami Arimoto, “Cell-Plate Line Connection Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM’s”, IEEE Journal of Solid State Circuits, vol. 27, No.4, pp.597-602, April 1992.
[2] Takashi Kono and Takeshi Hamamoto, “A Precharged-Capacitor-Assisted Sensing (PCAS) Scheme with Novel Level Controllers for Low-Power DRAM’s”, IEEE Journal of Solid State Circuits, vol. 35, No.8, pp.1179-1185, August 2000.
[3] Tadaaki Yamauchi, Fukashi Morisita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki and Tsutomu Yoshihara, “High-Performance Embedded SOI DRAM Architecture for the Low-Power Supply”, IEEE Journal of Solid State Circuits, vol. 35, No.8, pp.1169-1177, August 2000.
[4] Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata and Kazutami Arimoto, “SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories”, IEEE Journal of Solid State Circuits, vol. 31, No.4, pp.586-591, April 1996.
[5] Kiyoo Itoh, Katsuro Sasaki and Yoshinobu Nakagome, “Trends in Low Power RAM Circuit Technologies”, Proceeding of the IEEE, vol. 83, No.4, pp.524-543, April 1995.
[6] Kyuchan Lee, Changhyun Kim, Dong-Ryul Ryu, Jai-hoon Sim, Sang-bo Lee, Byung-sik Moon, Keum-Yong Kim, Nam-Jong Kim, Seung-Moon Yoo, Hongil Yoon, Jei-Hwan Yoo and Soo-In Cho, “Low-Voltage, High-Speed Circuit Design for Gigabit DRAM’s”, IEEE Journal of Solid State Circuits, vol. 32, No.5, pp.642-648, May 1997.
[7] Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume and Kazutami Arimoto, “Low Voltage Circuit Design Techniques for Battery-Operated and/or Giga-Scale DRAM’s”, IEEE Journal of Solid State Circuits, vol. 30, No.11, pp.1183-1188, November 1995.
[8] Daisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe and Kazunori Ohuchi, “Word-Line Architecture for Highly Reliable 64-Mb DRAM”, IEEE Journal of Solid State Circuits, vol. 27, No.4, pp.603-609, April 1992.
[9] Goro Kitsukawa, Kiyoo Itoh, Ryoichi Horo, Yoshiki Kawajiri, Takao Watanabe, Takiyuki Kawahara, Tetsuro Matsumoto and Yutaka Kobayashi, “A 1-Mbit BiCMOS DRAM Using Temperature-Compensation Circuit Techniques”, IEEE Journal of Solid State Circuits, vol. 24, No.3, pp.597-602, June 1989.
[10] Goro Kitsukawa, Kazumasa Yangisawa, Yutaka Kobayashi, Yoshitaka Kinoshita, Tatsuyuki Ohta, Tetsu Udagawa, Hitoshi Miwa, Hiroyuki Mitazawa, Yoshiki Kawajiri, Yoshiaki Ouchi, Hiromi Tsukada, Tetsuro Matsumoto and Kiyoo Itoh, “A 23-ns 1-Mbit BiCMOS DRAM”, IEEE Journal of Solid State Circuits, vol. 25, No.5, pp.1102-1111, Octobor 1990.
[11] Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, and Kazuyasu, “A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM’s”, IEEE Journal of Solid State Circuits, vol. 29, No.4, pp.432-440, April 1994.
[12] R. E. Scheuerlein, Y. Katayama, Y. Sakaue, A. Satoh, T. Sunaga, T. Yoshikawa, K. Kitamura and S. H. Dhong, “A Pulsed Sensing Scheme with A Limited Bit-Line Swing”, IEEE Journal of Solid State Circuits, vol. 27, No.4, pp.678-682, April 1992.
[13] I. Naritake, T. Sugibayashi, S. Utsugi and T. Murotani, “A Crossing Charge Recycle Refresh Scheme with A Separated Driver Sense-Amplifier for Gb DRAMs”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 101-102, 1995.
[14] Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana and Katsuyuki Sato, “A 29-ns 64-Mb DRAM with Hierarchical Array Architechture”, IEEE Journal of Solid State Circuits, vol. 31, No.9, pp.1302-1307, April 1992.
[15] Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi and Fujio Masuoka, “A 33-ns 64-Mb DRAM ”, IEEE Journal of Solid State Circuits, vol. 26, No.11, pp.1498-1505, November 1991.
[16] Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura and Shigeru Honjo, “A 9-ns 1-Mb CMOS SRAM ”, IEEE Journal of Solid State Circuits, vol. 24, No.5, pp.1219-1225, October 1989.
[17] Hiroyuki Yamauchi, Toshikazu Suzuki, Akihiro Sawada, Tohru Iwata, Toshiaki Tsuji, Masashi Agata, Takashi Taniguchi, Yoshinori Odake, Kazuyuki Sawada, Teruhito Ohnishi, Masanori Fukumoto, Tsutomu Fujita and Michihiro Inoue, “A Circuit Technology for High-Speed Battery-Operated 16-Mb CMOS DRAM’s”, IEEE Journal of Solid State Circuits, vol. 28, No.11, pp.1084-1091, November 1993.
[18] Betty Prince, “Semiconductor Memories”, John Willy & Son Ltd., 1991.
[19] Doris Keitel-Schulz and Norbert Wehn, “Embedded DRAM Development: Technology, Physical Design, and Application Issues”, IEEE Design & Test of Computers, vol. 18, No. 3, pp.7-15, May-June 2001.
[20] S. Okhonin, M. Nagoga, J. M. Sallese and P. Fazan “A SOI Capacitor-less 1T-DRAM concept”, IEEE International SOI Conference, pp.153-154, October 2001.
[21] S. Okhonin, M. Nagoga, J. M. Sallese and P. Fazan “A Capacitor-Less 1T-DRAM cell”, IEEE Electron Device Letters, vol. 23, No.2, February 2002.
[22] Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh, “An Experimental 1.5-V 64-Mb DRAM”, IEEE Journal of Solid State Circuits, vol. 26, No.4, pp.465-472, April 1991.
[23] Lee C.L., Wagiran R., Suparjo B.S. and Sidek R., “The Design of Low-Power CMOS Pipelined-Burst SRAM”, ICSE2000 Proceedings, pp. 241-244, November 2000.
[24] Raymond Y. V. Chilk and C. Andre T. Salama, “Design of a 1.5V Full-Swing Bootstrapped BiCMOS Logic Circuit”, IEEE Journal of Solid State Circuits, vol. 30, pp.972-978, September 1995.
[25] Sherif H. K. Embabi, Abdellatif Bellaouar and Kazi Islam, “A Bootstrapped Bipolar CMOS Gate for Low-Voltage Applications”, IEEE Journal of Solid State Circuits, vol. 30, No.4, pp.47-53, January 1995.
[26] Kiat-Seng Yeo, Jian-Guo Ma and Manh-Anh Do, “Ultra-Low-Voltage Bootstrapped CMOS Driver for High Performance Applications”, Electronic Letters, vol. 36, No.8, pp.706-708, April 2000.
[27] J. H. Lou and J. B. Kuo, “A 1.5-V Full Swing Bootstrapped CMOS Large Capacitive -Load Driver Circuit for Low Voltage CMOS VLSI”, IEEE Journal of Solid State Circuits, vol. 32, No.1, pp.119-121, January 1997.
[28] Y. Moisiadis, I. Bouras, A. Efthymiou and C.Papadas, “Fast 1V bootstrapped inverter suitable for standard CMOS technologies”, Electronic Letters, vol. 35, No.2, pp.109-111, January 1999.
[29] Mircea R. Stan, “Low-Power CMOS with subvolt Supply Voltages”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, No.2, pp.394-400, April 2001.
[30] Sang H. Dhong, Nichy Chau-Chun Lu, Wei Hwang and Stephen A. Parke, “High speed sensing scheme for CMOS DRAM’s”, IEEE Journal of Solid State Circuits, vol. 23, No.1, pp.34-40, February 1988.
[31] Jung-Won Suh, Kwang-Myoung Rho, Chan-Kwang Park and Yo-Hwan Koh, “Offset-Trimming Bit-Line Sensing Scheme for Gigabit-Scale DRAM’s”, IEEE Journal of Solid State Circuits, vol. 31, No.7, pp.1025-1028, July 1996.
[32] Yusuke Ohtomo, Hirotoshi Sawada, Terukazu Ohno, Yutaka Sakabara, Yasuhiro Sato, Takako Ishihara, Shinji Matsuoka and Masakazu Shimaya, “A Low-Power Multi-Gigabit CMOS/SIMOX LSI Design Using Two Power Supply Voltages”, Symposium on VLSI Circuits Digest of Technical Papers, pp.25-26, June 1999.
[33] Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura and Shigeru Honjo, “A 9-ns 1-Mb CMOS SRAM ”, IEEE Journal of Solid State Circuits, vol. 24, No.5, pp.1219-1225, October 1989.
[34] Hiroyuki Yamauchi, Toshikazu Suzuki, Akihiro Sawada, Tohru Iwata, Toshiaki Tsuji, Masashi Agata, Takashi Taniguchi, Yoshinori Odake, Kazuyuki Sawada, Teruhito Ohnishi, Masanori Fukumoto, Tsutomu Fujita and Michihiro Inoue, “A Circuit Technology for High-Speed Battery-Operated 16-Mb CMOS DRAM’s”, IEEE Journal of Solid State Circuits, vol. 28, No.11, pp.1084-1091, November 1993.