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研究生:陳易緯
研究生(外文):Yi-Wei Chen
論文名稱:匯流排資料寬度轉換之先進先出記憶體與數位無線耳機基頻控制器之類比前端介面
論文名稱(外文):An FIFO Memory Design for Data Exchange Bus and Analog Front-end of Digital Cordless Headset Baseband Controller
指導教授:王朝欽
指導教授(外文):Chua-Chin Wang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:69
中文關鍵詞:直流電壓轉換器類比前端先進先出記憶體
外文關鍵詞:DC-DC converteranalog front-endFIFO memory
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本論文共涵蓋三個不同的主題:第一部份為匯流排資料寬度轉換之先進先出記憶體的實作,我們提出一個FIFO記憶體的架構能使用於兩個不同資料寬度的裝置間,不需要仲裁模組去決定輸出或輸入的順序,因此延遲可以大為減少。
第二部份為數位無線耳機基頻控制器之類比前端介面的實作,此類比數位介面整合IC,主要的功能就是提供數位資訊與類比訊號的溝通界面,將類比訊號轉換成8位元數位訊號後再由後端控制器進一步的處理,並且可以將8位元的數位語音資訊轉換成為類比的聲音資訊,並內建含致能訊號的震盪器。
第三部份為內建電壓偵測之直流電壓轉換器的實作,此電路能夠將1.5V的直流電壓轉為2.7V輸出。因此一個系統靠著這個電路可以只用一顆乾電池便可啟動,電路內部同時內建一個電壓偵測器能指出目前輸出電壓的情形。


Three different chip design topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of an FIFO memory design for 8-to-32 data exchange bus. An FIFO memory architecture is proposed to be utilized in data exchange between processing units which possess non-homogeneous bus widths. Neither arbiter logics nor modules are required in such a design to determine input sequences or output sequences. Hence, the delay is drastically shortened.
The second topic is focused on the implementation of an analog front-end of digital cordless headset baseband controller. The integrated analog and digital interface IC provides an interface for analog and digital communication. It converts an analog signal into an 8-bit digital signal, which will be processed by the baseband controller. It also converts an 8-bit digital voice data into an analog voice signal. In addition, a built-in oscillator is included in the design, which provides a global clock signal.
The third topic is to carry out an DC/DC converter with a built-in voltage detector. The converter can convert 1.5V input voltage to 2.7V output voltage. A portable system can use only one single battery to power on by this circuit. It also contains a voltage detector to indicate whether the output voltage meets the pre-determined level.


摘要i
Abstractii
第一章 簡介1
1.1論文動機與目的1
1.2相關研究討論2
1.3論文大綱4
第二章 匯流排資料寬度轉換之先進先出記憶體5
2.1簡介5
2.2研究動機5
2.3架構原理與電路設計9
2.3.1 8-to-32 FIFO記憶體架構9
2.3.2 32-to-8 FIFO記憶體架構13
2.4效能分析14
2.5效能模擬與晶片佈局15
2.5.1 8-to-32 FIFO 晶片實現16
2.6結論20
第三章 數位無線耳機基頻控制器之類比前端介面21
3.1簡介21
3.2研究動機21
3.3系統雛型驗證22
3.4架構原理與電路設計25
3.4.1 設計原理與方法25
3.4.2 電路架構26
3.4.3 4-channel ADC27
3.4.4 8-bit DAC29
3.4.5 Oscillator32
3.5模擬結果33
3.5.1 4-channel ADC33
3.5.2 8-bit DAC35
3.5.3 Oscillator35
3.6佈局36
3.7測試結果39
3.7.1 4-channel ADC39
3.7.2 8-bit DAC41
3.7.3 Oscillator42
3.7.4 量測結果44
3.8結論45
第四章 內建電壓偵測之直流電壓轉換器47
4.1簡介47
4.2研究動機47
4.3架構原理與電路設計48
4.4模擬結果與晶片佈局51
4.4.1 模擬結果51
4.4.2 晶片實現52
4.5測試結果55
4.6結論58
第五章 結論59
參考文獻60
附錄63


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