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研究生:邱自強
研究生(外文):Chih-Chiang Chiu
論文名稱:低溫度敏感性4kb動態隨機存取記憶體自我更新電路與快速半波NOR-NORPLA架構
論文名稱(外文):4kb DRAM with an Temperature-Insensitive Self-Refreshing Circuitry and Fast Half-Swing NOR-NOR PLA Architecture
指導教授:王朝欽
指導教授(外文):Chua-Chin Wang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:74
中文關鍵詞:低溫度敏感性半波自我更新
外文關鍵詞:Self-RefreshingHalf-SwingTemperature-Insensitive
相關次數:
  • 被引用被引用:0
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  • 收藏至我的研究室書目清單書目收藏:0

本論文的第一部份,提出一新的架構其自我更新週期在DRAM待機模式下會隨溫度動態改變以減少功率消耗。所提出之電路藉由監看因漏電流所造成記憶單元的資料遺失情況來調整更新週期,因而自我更新週期將隨溫度改變而改變,達到省電之目的。
本論文的第二部分,提出兩個運用於NOR-NOR PLA的CMOS快速半波電路。一個附加的1/2VDD電壓源和一個傳輸閘被插入兩個NOR平面之間,用來消除追繞問題和縮短輸出上升延遲和下降延遲時間,提高運算速度。


The first part of this thesis presents a novel design for DRAMs to provide self-refreshing cycles which vary with temperature dynamically to reduce power dissipation in a standby mode. The proposed design monitors the data loss of a memory cell which is resulted from the leakage current, and then adjusts the period of the self-refreshing cycles.
The second part presents two fast half-swing CMOS circuits for NOR-NOR PLA implementation. An additional 1/2VDD voltage source and buffering transmission gates are inserted between the NOR planes of PLAs to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced.


摘要i
Abstractii
第一章 簡介1
1.1 前言1
1.2 先前相關文獻探討2
1.2.1 自我更新功率消耗2
1.2.2 相關PLA架構3
1.3 論文目的3
1.4 論文大綱4
第二章 具有適應性更新週期的動態隨機存取記憶體模組5
2.1 簡介5
2.2 論文製程選擇說明7
2.3 架構簡介8
2.3.1 適應性震盪器8
2.3.2 晶片架構12
2.3.3 DRAM基本架構13
2.3.4 DRAM之操作16
2.3.5 時序控制器18
2.3.6 感測放大器21
2.3.7 位址閂鎖器23
2.3.8 位址選擇器24
2.3.9 內部位址計數器24
2.3.10 記憶單元電容佈局架構24
2.4 模擬結果25
2.4.1 適應性震盪器模擬25
2.4.2 晶片模擬28
2.5 晶片量測結果33
2.5.1 適應性震盪器更新週期量測33
2.5.2 晶片DRAM讀寫測試37
2.5.3 自我更新模式測試40
2.6 結論43
第三章 快速半波NOR-NOR PLA架構45
3.1 簡介45
3.2 半波快速NOR-NOR PLA設計47
3.2.1 一般NOR-NOR PLA電路架構47
3.2.2 半波NOR-NOR PLA電路架構48
3.2.3 修改型半波Dynamic NOR-NOR PLA電路架構51
3.3 速度與面積overhead分析54
3.3.1 速度分析54
3.3.2 面積overhead分析54
3.4 模擬分析55
3.4.1 速度模擬55
3.4.2 功率消耗模擬62
3.4.3 修改型半波Dynamic NOR-NOR PLA電路模擬63
3.5 半波電路架構CLA加法器晶片測試66
3.6 結論69
第四章 結論70
參考文獻71


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