臺灣博碩士論文加值系統

本論文包含兩個主題，第一個主題是可程式延遲鎖相迴路倍頻器主要運用於射頻前端之本地震盪源，第二個主題是無ROM之直接數位式頻率合成器主要運用於產生完美參考時脈或基頻信號之數位調變與解調。
可程式延遲鎖相迴路倍頻器是使用CMOS製程，其優點為不需要任何之電感元件，且輸出時脈倍數可利用數位信號控制來達成，頻率倍數為7´ ~ 10´的參考時脈頻率，此晶片實現是使用TSMC 0.25 mm的CMOS製程，供應電壓2.5 V。最後晶片實際量測時，輸出頻率為1.0 GHz ~ 1.5 GHz，晶片操作於1.5 GHz時，最大功率消耗為58.2 mW。
無ROM之直接數位式頻率合成器主要是使用三角函數四倍角公式來實現，其系統層級模擬，寄生信號(spurious tones)抑制效能為-130 dBc，解析度高達13位元，整個頻率合成器誤差極值之發生點，亦同時利用數學方法加以佐證。

This thesis includes two topics. The first topic is a programmable DLL-based frequency multiplier, which can be a local oscillator in RF applications. The second one is a ROM-less direct digital frequency synthesizer to serve as a good reference clock or to be used in digital modulation and demodulation.
A CMOS local oscillator using a programmable DLL-based frequency multiplier is presented. In this work, low-Q on-chip inductors are not needed. The clock of the output frequency is digitally controllable, which is ranged from 7´ to 10´ of an input reference clock. The design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The output frequency range of the physical chips measurement is about 1.0 GHz ~ 1.5 GHz. Maximum power dissipation is 58.2 mW at 1.5 GHz output.
A ROM-less direct digital frequency synthesizer (DDFS) employing trigonometric quadruple angle formula is presented. In a system-level simulation, the spurious tones performance is suppressed to be lower than -130 dBc. The resolution is up to 13 bits. The maximum error is also analyzed mathematically to meet the simulation results.

摘 要i
Abstractii
第一章 簡介1
1.1研究動機1
1.2論文目的4
1.3論文大綱5
第二章 先前相關文獻探討6
2.1簡介6
2.2頻率合成器與傳送接收機7
2.2.1接收機的架構7
2.2.2傳送機的架構9
2.2.3結論10
2.3頻率合成器之相位雜訊與寄生信號11
2.3.1頻率合成器與傳送機接收機11
2.3.2相位雜訊12
2.3.3寄生信號14
2.4鎖相迴路架構及其相關研究發展16
2.4.1鎖相迴路之工作原理及特性16
2.4.2單石整合諧振器(Monolithic Integrated LC-tank)18
2.4.3製程強化電感20
2.4.4整合型環型壓控震盪器21
2.5直接數位式頻率合成器22
2.5.1直接數位式頻率合成器之工作原理22
2.5.2直接數位式頻率合成器特性24
2.6直接數位式頻率合成器之雜訊26
2.6.1相位累加器位元捨棄效應26
2.6.2唯讀記憶體有限資料長度效應27
2.7結論28
第三章 可程式化延遲鎖相迴路倍頻器29
3.1簡介29
3.2延遲鎖相迴路的特性與工作原理30
3.2.1可程式化延遲鎖相迴路倍頻器之運作30
3.2.2時間抖動累積效應32
3.3延遲鎖相迴路之效能34
3.3.1寄生信號34
3.3.2相位雜訊36
3.4電路設計40
3.4.1相位頻率偵測器40
3.4.2充電泵與迴圈濾波器42
3.4.3壓控延遲鏈45
3.4.4正緣收集器47
3.4.5時脈產生器49
3.5佈局後電路模擬 (Post-layout simulation)51
3.6晶片量測54
第四章 無ROM之直接數位式頻率合成器57
4.1簡介57
4.2無ROM式直接數位式頻率合成器58
4.2.1三角函數之一階四倍角近似值法58
4.2.2三角函數之二階四倍角近似值法62
4.2.3二階四倍角近似值法之數學分析63
4.3直接數位式頻率合成器之數位系統實作65
4.3.1無ROM之直接數位式頻率合成器架構65
4.3.2系統層次模擬65
4.3.3 FPGA模擬與驗證67
4.4結論70
第五章 結論與相關成果71
參考文獻72
附錄75

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