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研究生:陳國龍
研究生(外文):Kuo-Long Chen
論文名稱:使用具有低功率止擾器雙門檻電壓之6-電晶體靜態記憶體與可程式化鎖相迴路式倍頻器之晶片設計與實作
論文名稱(外文):IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier
指導教授:王朝欽
指導教授(外文):Chua-Chin Wang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:61
中文關鍵詞:雙門檻電壓靜態記憶體鎖相迴路
外文關鍵詞:SRAMPLLDual Threshold Voltage
相關次數:
  • 被引用被引用:2
  • 點閱點閱:154
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  • 收藏至我的研究室書目清單書目收藏:0
本論文共涵蓋兩個不同的主題:第一部份為使用雙門檻電壓之6-電晶體靜態記憶體及低功率止擾器的實作。本晶片設計之重點為使用雙門檻電壓電晶體的SRAM記憶單元,其優點為加快記憶體的存取速度同時維持資料的完整。並提出背對背止擾器 (Quenchers) 以消除記憶體在輸出資料線上大電流所造成的不必要之震盪現象。
第二部份為可程式化鎖相迴路式倍頻器,使用鎖相迴路的架構及可程式化除頻器來實現,可提供高速數位電路的同步時脈訊號,亦可使用在無線通訊系統上,例如本地震盪器。
Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers.
The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. A synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators.
摘要……i
Abstractii
第一章 簡介1
1.1研究動機與目的1
1.2先前相關文獻討論2
1.3論文大綱4
第二章 使用雙門檻電壓之6-電晶體靜態記憶體及低功率止擾器5
2.1概論5
2.2架構簡介9
2.2.1 SRAM記憶單元9
2.2.2 止擾器 (Quenchers)13
2.2.3 內建自我測試考量14
2.2.4 SRAM架構16
2.3模擬結果20
2.3.1 SRAM記憶單元模擬結果20
2.3.2 止擾器模擬結果21
2.3.3 SRAM模擬結果21
2.3.4 內建自我測試模擬結果25
2.4測試結果與晶片佈局26
2.4.1 SRAM讀寫測試26
2.4.2 內建自我測試功能量測31
2.4.3 晶片佈局32
2.5結論34
第三章 可程式化鎖相迴路式倍頻器36
3.1概論36
3.2架構簡介38
3.2.1 壓控震盪器38
3.2.2 相位頻率偵測器40
3.2.3 電荷幫浦器與迴路濾波器41
3.2.4 可程式化除頻器44
3.3模擬結果與晶片佈局48
3.3.1 模擬結果48
3.3.2 晶片佈局51
3.4測試結果53
3.5結論56
第四章 總結57
參考文獻58
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