跳到主要內容

臺灣博碩士論文加值系統

(3.233.217.106) 您好!臺灣時間:2022/08/17 22:05
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:黃乙安
研究生(外文):Yi-An Huang
論文名稱:實現無線手機可用之4乘8鍵盤掃描解碼器具有RC5的傳輸協定及高速靜態記憶體之使用電流感測器
論文名稱(外文):A Cell-Based Design Solution of 4x8 Scanning Decoder Using RC5 Protocol for Wireless Handsets and A High-Performance Current Sense Amplifiers for SRAMs
指導教授:王朝欽
指導教授(外文):Chua-Chin Wang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:48
中文關鍵詞:電流感測器RC5盤掃描解
外文關鍵詞:RC5Current Sense AmplifiersScanning Decoder
相關次數:
  • 被引用被引用:0
  • 點閱點閱:338
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:1

在論文中的第一部分我們提出一個自建元件(Cell)的方式實現4乘8鍵盤掃瞄解碼器具有RC5的傳輸協定的電路。其為一沒有內嵌式微處理器及內部唯讀記憶體鍵盤掃瞄解碼器,並且利用RC5的傳輸協定作為與手機連接的橋樑,藉此減少手機控制IC的面積節省成本。此外功率消耗也是影響可攜型設備工作時間的重要考量。此晶片就有上述的兩個優點。
第二部分是討論使用電流感測器的高速及低功率靜態記憶體。靜態記憶體目前廣泛的應用在電腦系統及各式可攜式裝置當中,是一種可以高速存取的記憶體介面,而因為低功率與高速之要求下,我們以電流感測器來取代傳統之電壓感測式放大器 (Sense Amplifier) ,其操作速度可達1GHz。


The first topic of this thesis is a cell-based design solution of 4×8 scanning decoder using RC5 protocol for DECT handsets. It is a keypad scanner ASIC without any embedded microprocessor nor internal ROMs. The keypad scanner uses RC5 transfer protocol which is compatible with remote control and wireless handsets. The keypad scanner built in the handsets must meet the requirement of low power consumption and small die size to avoid shortening the battery lift and increasing chip cost. The proposed ASIC design possesses both of the required advantages.
The second topic is a high-performance SRAM using current sense amplifier. Current sensing in SRAMs is very promising method to achieve high speed operations in low-voltage applications. This topic present a current sense amplifier circuit as well as its simulation results.


目錄
第一章簡介1
1.1研究動機1
1.2先前文獻與論文目的2
1.3論文大綱3
第二章以自建元件的方式實現無線手機可用之4乘8鍵盤掃瞄解碼器具有RC5的傳輸協定4
2.1概論4
2.2架構簡介5
2.2.1Key Scanning的架構說明:5
2.2.2Key Scanning的動作流程圖說明:7
2.2.3Key Scanning的工作原理:9
2.2.4RC5的傳輸協定說明:11
2.2.5功率消耗考量的設計12
2.4設計流程與模擬結果13
2.4.1模擬結果14
2.4.2效能比較20
2.5結論21
第三章使用電流感測器的高速及低功率靜態記憶體22
3.1概論22
3.2架構簡介23
3.2.1SRAM的架構說明:23
3.2.2電流放大器的電路分析 :26
3.2.3電流感測放大器說明與功能模擬:27
3.2.4使用電流感測放大器來實作16×8位元的靜態記憶體29
3.3結論31
第四章總結32
參考文獻33
附錄 36
A.此部分為Keypad完整之Verilog原始程式碼36
B.此部分為Keypad完整之測試Verilog原始程式碼43
C.自建元件的佈局圖45


[1]R.X. Gu, and M. I. Elmasry, “All-N-logic high speed true-single-phase dynamic CMOS logic,” IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 221-229, Feb. 1996.
[2]Philips Semiconductors, “PCA84C122 demo unit,” Reading Application Note, ETV/AN91002, Apr. 1991.
[3]Philips Semiconductors, “PCA8521 infrared remote control transmitter,” Reading: DATA SHEET, Product sepecification, June 1999.
[4]N.-S. Tan, Y.-H. Gao and M.-F. Gong, “A new design method for encoding and decoding circuit,” 1991 Inter. Conference on Circuit and Systems, vol. 1, pp. 442-444, June 1991.
[5] C.-C. Wang, C.-J. Huang, and K.-C. Tsai, “A 1.0 GHz 0.6-um 8 bit carry lookahead adder using PLA-styled all-N-Transistor logic,” IEEE Trans. Circuits and Systems, PartII: Analog and Digital Signal Processing, vol. 47, no. 2, pp. 133-135, Feb. 2000.
[6] C.-C. Wang, P.-M. Lee, Y.-A. Huang, and R. Hu, “A cell-based design solution of 4 x 8 scanning decoder using RC5 protocal for DECT handsets,” ICICS, pp.271-276, Oct. 2001.
[7] 蔡坤助, “前瞻性微處理機之以PLA形式全N電晶體邏輯設計之1.0GHz 0.6um前看進位加法器與64-bit平行比較器”, 中山大學電機工程學系碩士論文,民國九十年六月。
[8]李榮欽, “32位元1.25GHz樹狀架構前瞻式進位加法器與離散餘弦轉換之晶片設計與實作” ,中山大學電機工程學系碩士論文,民國九十年六月。
[9]M.-M. Khellah and M. I. Elmasry, ”A low-Power High-Performance Current-Mode Multiport SRAM,” IEEE Trans. On VLSI systems, vol. 9, no.5. pp. 590-598, Oct. 2001.
[10]B. Wicht, S. Paul, and D. Schmitt-Landsiedel, “Analysis and compensation of the bitline muliplexer in SRAM current sense amplifiers,” IEEE J. Solid-State circuits, vol. 36, no.11, pp1745-1755, Nov. 2001.
[11]E. Seevinck, P.J. van Beers, and H. Ontrop, “Current-mode techniques for high-speed VLSI circuits with application to current amplifier for CMOS SRAMs,” IEEE J. Solid-State Circuits, vol. 26, pp.525-536, Apr. 1991.
[12]N. Shibata, “Current sense amplifiers for low-voltage memories,” IEICE Trans. Electron., vol. E79-C, no. 8, pp. 1120-1130, Aug. 1996.
[13]Tegze P. Haaszti, “CMOS memory circuits,” ISBN 0-7923-7950-0, Reading: pp.164-275, pp.328-334 Kluwer Academic Publishers, 2000.
[14]M. Nomura et al, “A 500-MHz, 0.4-um CMOS, 32×32 3-Port register file,” Proc. IEEE Custom Integrated Circuits Conf, pp.151-154, 1995.
[15]H. Nambu, “A 1.8ns access, 550MHz 4.5Mb CMOS SRAM,” in Proc. Int. Solid-State Circuits Conf., pp. 360-361, Feb. 1998,
[16]J. Alowersson and P. Andersson, “SRAM cells for low-power write buffer memories,” in Proc. IEEE Low-Power Electronics, pp. 61-62, 1995.
[17]K. Ishibashi et al., “A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers,” IEEE J. Solid-State Circuits, vol.30, pp.480-486, Apr. 1995.
[18]B. Wicht, S. Paul, D. Schmitt-Landsiedel, and A. Sanders, “SRAM current-sense amplifier with fully-compensated bit-line multiplexer,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp.172-173, Feb. 2001.
[19]J. Alowersson, “A CMOS circuits technique for high-speed RAMs,” IEEE Int. ASIC conf., pp.243-246,1993
[20]K. Itoh et al., “Trends in low-power RAM circuits technologies,”Proc. IEEE, vol. 83, pp524-543, Apr. 1995.
[21]Paul R. Gray and Robert G.Meyer, “Analysis and Design of Analog Integrated circuits,” Reading: pp281-287, John Wiley & Sons Inc, 1993

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top