臺灣博碩士論文加值系統

晶圓針測（Wafer Probing）接續於晶圓製造之後，屬半導體業之前段製程。交期達成率為該產業最重視之目標，但設置時間、週期時間以及產出量等，亦為必要之衡量指標。以生產型態而言，其屬零工型生產之一種，但多樣化的產品和機台類型，以及兩者間複雜的對應關係，再加上來到不穩定、設置序列相關等特性之考量，使其複雜度較典型零工型生產型態高出許多。
為彌補單一派工法則只能使某特定排程目標接近最佳之缺點，本研究採用整合型之派工方法解決此排程問題，也就是多屬性派工方法。首先針對現實中所考量之多項目標，將多項績效值整合為單一績效值；進而考量針測業中待測品所具有之多項屬性，包括緊急程度(急件或一般件)、加工時間、設置時間、等待時間…等等，作為派工法則之發展依據。針對整合型之多屬性派工方法，過去曾有學者提出參數化派工之方式，本研究將以此方法為基礎，並將混合型實驗運用於其中之權重設定部分，利用混合型實驗中屬性與績效指標之分析，得知各屬性對績效指標之影響程度，藉以設定各屬性之權重，用以表示各屬性之重要程度。最後利用eM-Plant模擬軟體建構模擬模式、並以Design-Expert軟體進行實驗設計。於多種環境下，藉由混合型實驗中之迴歸方程式，分析各屬性與績效指標兩者間之關係；並針對多項實驗變因，分析各變因對績效指標之影響程度；此外亦於多種環境下，比較既有派工方法與本研究所提派工法則之績效表現。
經由模擬分析結果發現來到間隔時間為影響各績效指標之最主要因素，其次則為派工法則；且各屬性與各派工法則對各項績效指標之影響程度均會隨來到間隔時間等環境變因之改變而變動。實驗結果亦顯示，若以整體績效而言，將本研究所提之派工法則與其他派工方法相比，本研究之方法於大多數環境中均具有最佳之表現。

摘要 i
謝誌 ii
目錄 iii
圖目錄 vi
表目錄 viii
第一章 緒論 1
1.1 研究背景與動機 1
1.2 研究目的 3
1.3 研究範圍 3
1.4 研究步驟與方法 4
第二章 半導體晶圓針測廠簡介 6
2.1半導體產業之發展 6
2.2 晶圓針測作業之介紹 9
2.2.1 晶圓針測相關設備 10
2.2.2 晶圓針測作業流程 13
2.3 晶圓針測排程特性 15
第三章 文獻回顧 19
3.1 現場排程技術文獻 19
3.1.1 最佳化技術 19
3.1.2派工法則（Dispatching）與啟發式解法（Heuristics） 20
3.1.3 人工智慧技術 22
3.2 多屬性與多目標排程文獻 23
3.2.1多目標決策問題相關文獻 23
3.2.2傳統單一/平行機台之多目標排程文獻 26
3.2.3一般流線(Flow Shop)/零工型(Job Shop)之多目標排程文獻 27
3.3半導體測試文獻探討 30
3.3.1 晶圓針測與最終測試之排程特性 30
3.3.2 半導體測試排程相關文獻 31
第四章 結合混合型實驗之多屬性派工法則 34
4.1 研究問題之定義 34
4.1.1 假設條件 34
4.1.2 績效評估指標 35
4.2參數化派工法則( Parameterized Dispatching Rule, PDR) 37
4.2.1 多屬性派工 37
4.2.2 參數化派工法則之架構 38
4.3屬性之決定 40
4.3.1 屬性之選擇 40
4.3.2 屬性之正規化 43
4.4權重之制訂 44
4.4.1 混合型實驗 47
4.4.2混合型實驗於權重制定之應用 52
第五章 實驗設計與模擬分析 57
5.1實驗目的 57
5.2實驗系統說明 57
5.2.1系統描述與假設 57
5.2.2績效指標 61
5.3 實驗變因 63
5.3.1控制變因 63
5.3.2環境變因 64
5.4 模擬結果分析 66
5.4.1混合型實驗分析 66
5.4.2 全因子實驗分析 90
5.4.3 單因子(派工法則) 實驗分析 107
5.5 結論 113
第六章 結論與建議 115
6.1 結論 115
6.2 建議 117
參考文獻 118
附錄A 122
附錄B 143

1.吳仲昇, ”遺傳演算法在晶圓針測排程問題之應用,” 國立清華大學工業工程研究所論文, 1996.
2.李威亭, ”邏輯IC最終測試廠之測試機台排程研究,” 國立清華大學工業工程與工程管理研究所論文, 2000.
3.林大欽, ”邏輯IC測試廠短期生產排程之探討,” 國立清華大學工業工程研究所論文, 1997.
4.林則孟, 系統模擬─理論與應用, 滄海書局, 2001.
5.林則孟、吳仲昇, “半導體晶圓製造廠測試區之模擬基礎的排程研究,” 國科會研究報告NSC85-2221E-007-048, 1996.
6.胡朝鈞, “多資源限制之智慧型排程-以半導體測試作業為例,” 中原大學工業工程研究所論文, 2001.
7.陳安怡, “IC 最終測試廠排程問題,” 國立交通大學工業工程與管理研究所論文, 2001.
8.陳淑靜, ”晶圓針測廠生產規劃模式之構建,” 國立交通大學工業工程與管理研究所論文, 1997.
9.湯景富, “半導體廠測試區生產規劃模式之構建,” 國立交通大學工業工程與管理研究所論文, 1995.
10.黃聖智, “半導體針測區之互動式排程研究,” 國立清華大學工業工程與工程管理研究所博士論文, 1999.
11.楊明賢, “晶圓針測廠等效平行機台排程問題之研究：模式、演算法與應用,” 國立交通大學工業工程與管理研究所博士論文, 2001.
12.廖靜詩, “運用網路方法於晶圓針測排程規劃之研究,” 國立交通大學工業工程與管理研究所論文, 2001.
13.鄧豐毅, “半導體針測區現場作業排程分析,” 國立清華大學工業工程研究所論文, 1998.
14.謝有信, “半導體生產後段製程之晶圓測試部份的派工問題研究,” 國立清華大學工業工程研究所論文, 1997.
15.羅盛豪, “運用基因法則構建半導體測試區現場排程模式,” 國立交通大學工業工程與管理研究所論文, 1996.
16.蘇志浩, “以限制驅導式為基之半導體最終測試廠短期生產排程模式,” 國立清華大學工業工程與工程管理研究所論文, 1999.
17.Adachi, T., Moodies, C., and Talavage, J. J., “A pattern-recognition based method for controlling a multi-loop production system,” International Journal of Production Research, Vol. 26, No. 12, pp. 1943-1957, 1988.
18.Chen, H. N., “Optimizing multi-objective daily production plans for complex manufacturing facilities,” PhD. Thesis, Arizona State University, 2001.
19.Choi, R. H. and Malstrom, E. M., “Evaluation of traditional work scheduling rules in a flexible manufacturing system with a physical simulator,” Journal of Manufacturing Systems, Vol. 7, No. 1, pp. 33-45, 1988.
20.Chryssoluris, G., Dicke, K., and Lee, M., “An approach to short interval scheduling for discrete parts manufacturing,” International Journal of Computer Integrated Manufacturing, Vol.4, No.3, pp. 157-168, 1991.
21.Conway, R. W., Maxwell, W. L. and Miller L. M., Theory of Scheduling, Addison-Wesley, 1967.
22.Cornell, J. A., Experiments with Mixtures, John Wiley & Sons, 1981.
23.Dabbas, R. M., Chen, H. N., Fowler, J. W., and Shunk, D., “A combined dispatching criteria approach to scheduling semiconductor manufacturing systems,“ Computers and Industrial Engineering, Vol. 39, pp. 307-324, 2001.
24.Derringer, G., and Suich, R., “Simultaneous optimization of several response variables,” Journal of quality technology, Vol. 12, No. 4, pp. 214-219, October 1980.
25.Fry, T. D., Armstrong R. D. and Lewis, H., “A framework for single machine multiple objective sequencing research,” OMEGA International Journal of Management Science, Vol. 17, No. 6, pp.595-607, 1989.
26.Gangadharan, R. and Rajendran, C., “A simulated annealing heuristic for scheduling in a flow shop with bicriteria,” Computers and Industrial Engineering, Vol. 27, pp.473-476, 1994.
27.Grabot, B. and Geneste, L., “Dispatching rules in scheduling: a fuzzy approach,” International Journal of Production Research, Vol. 32, No. 4, pp. 903-915, 1994.
28.Jackson, J. R., “Simulation research on job shop production,” Naval Research Logistics Quarterly, Vol. 4, No. 4, pp. 287-295, 1957.
29.Lee, C. Y., Martin-Vega, L. A., Uzsoy, R. and Hinchman, J., “Implementation of a decision support system for scheduling semiconductor test operations”, Journal of Electronics Manufacturing, Vol. 3, No. 3, pp. 121-131, 1993.
30.Lee, S. M. and Jung, H. J., “A multi-objective production planning model in a flexible manufacturing environment,” International Journal of Production Research, Vol. 27, No. 11, pp. 1981-1992, 1989.
31.Li, D.-C. and She, I.-S., “Using unsupervised learning technologies to induce scheduling knowledge for FMSs,” International Journal of Production Research, Vol. 32, No. 9, pp. 2187-2199, 1994.
32.Montazeri, M. and Van Wassenhove, L. N., “Analysis of scheduling rules for an FMS,” International Journal of Production Research, Vol. 28, No. 4, pp. 785-802, 1990.
33.Montgomery, D. C., Design and Analysis of Experiments 4/E, John Wiley & Sons, 1997.
34.Nagar, A., Haddock, J. and Heragu, S., “Multiple and bicriteria scheduling: A literature survey,” European Journal of Operational Research, Vol. 81, pp. 88-104, 1995.
35.Ovacik, I. M. and Uzsoy, R., “Worst-case error bounds for parallel machine scheduling problems with bounded sequence-dependent setup times,” Operations Research Letters, Vol. 14, No. 5, pp. 251-256, 1993.
36.Perry, C. N. and Uzsoy, R., “Reactive scheduling of a semiconductor testing facility”, Fifteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium, pp. 191-194, 1993.
37.Ramesh, R. and Cary, J. M., “An efficient approach to stochastic jobshop scheduling: Algorithms and empirical investigations,” Computers and Industrial Engineering, Vol. 18, No. 2, pp. 181-190, 1990.
38.Randhawa, S. U. and Kuo, C. H., “Evaluating scheduling heuristics for non-identical parallel processors”, International Journal of Production Research, Vol.35, pp. 969-981, 1997.
39.Randhawa, S. U. and Smith, T. A., “An experimental investigation of scheduling non-identical, parallel processors with sequence-dependent set-up times and due dates”, International Journal of Production Research, Vol.33, No.1, pp. 59-69, 1995.
40.Sivakumar, A. I., “Multiobjective dynamic scheduling using discrete event simulation,” International Journal of Computer Integrated Manufacturing, Vol.14, No.2, pp. 154-167, 2001.
41.Sridhar J., and Rajendran C., “Scheduling in flowshop and cellular manufacturing systems with multiple objectives - A genetic algorithmic approach,” Production Planning and Control, Vol. 7, No. 4, pp.374-382, 1996.
42.Triantaphyllou, E. and Lin, C. T., “Development and evaluation of five fuzzy multiattribute decision-making methods,” International Journal of Approximate Reasoning, Vol. 14, Issue. 4, pp. 281-310, 1996.
43.Uzsoy, R., Church, L. K., Ovacik, I. M. and Hinchman, J., “Performance evaluation of dispatching rules for semiconductor testing operations,” Journal of Electronics Manufacturing, Vol. 3, pp. 95-105, 1993.
44.Uzsoy, R., Lee, C. Y. and Martin-Vega, L. A., “Scheduling semiconductor test operations: Minimizing maximum lateness and number of tardy jobs on a single machine”, Naval Research Logistics, Vol.39, pp. 369-388, 1992.
45.Uzsoy, R., Lee, C. Y., and Martin-Vega, L. A., “A review of production planning and scheduling models in the semiconductor industry, Part I: System characteristics, performance evaluation and production planning,” IIE Transactions, Vol. 24, No. 4, pp. 47-60, 1992.
46.Uzsoy, R., Martin-Vega, L. A., Lee, C. Y. and Leonard, P. A., “Production scheduling algorithm for a semiconductor test facility”, IEEE transactions on semiconductor manufacturing, Vol.4, No.4, pp. 270-280, 1991.
47.Uzsoy. R., Church, L. K., Ovacik, I. M., and Hinchman, J., “Dispatching rules for semiconductor testing operations: a computational study,” IEEE/CHMT Int. Elec. Manufacturing Technology Symposium, pp. 272-276, 1992.
48.Vairaktarakis, G. L. and Lee, C. Y. “The single-machine scheduling problem to minimize total tardiness subject to minimum number of tardy jobs,” IIE Transactions, Vol. 27, pp. 250-256, 1995.
49.Wroblewski, K. and Krawczynski, R., “Priority rules in production flow control,” Material Flow, Vol. 2, pp. 167-177, 1985.
50.Yang, J. and Chang, T. S., “Multiobjective scheduling for IC sort and test with a simulation testbed”, IEEE transactions on semiconductor manufacturing, Vol.11, No.2, pp. 304-315, 1998.
51.Yang, J., Chang, T. S., Chang, H. and Kao, J., “Optimization-based dynamic scheduling and its testbed for IC sort and test”, Proceedings of the 35th IEEE Conference on Decision and Control, Vol.3, pp. 2759-2762, 1996.