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研究生:戴列章
研究生(外文):Lieh-Chang Tai
論文名稱:半導體測試生產線之動態派工方法
論文名稱(外文):A Dynamic Dispatching Approach for Semiconductor Wafer Test
指導教授:林則孟林則孟引用關係
指導教授(外文):James T. Lin
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工業工程與工程管理學系
學門:工程學門
學類:工業工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:69
中文關鍵詞:晶圓針測晶片測試動態派工
外文關鍵詞:CP (Circuit Probing)Dynamic dispatchingWafer probingWafer test
相關次數:
  • 被引用被引用:2
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隨著半導體先進製程技術的蓬勃發展與激烈競爭(0.15um-> 0.13um-> 90nm), 在提供即時且快速的良率回饋以利製程改善的服務上, 晶片測試扮演了一個愈加重要的角色。 然而, 晶片測試生產線, 由於換線頻率的增高、進貨不穩定的到達以及急貨需優先上機等因素而顯得日趨複雜。 外加晶片測試現場異質化之特質(樣多量少, 流程與測試時間因產品種類有顯著之不同, 且有許多非等效性之機台), 以及生產線快速且不預期之狀態改變持續發生(如機台狀態、待測品優先度以及待測品數量與狀態), 是以, 在如此複雜且快速變動的生產環境下, 如何能同時兼顧多屬性之待測品並達成多屬性之排程目標(如最大達交率、急貨使命必達、最短生產週期時間和最少換線率), 發展一套即時之動態派工方法, 可以不論現場狀態如何改變, 實在是一項必要且重要的關鍵因素。 本研究所提出之派工方法, 主要是以事件導向(急件進入與機台待料)之反應式排程為主體, 再加上兩階段式派工方法(Lot ranking與Lot assignment)之構建, 可決定所有待測品之排程優先度以及適當之上機安排。 根據案例推導與實驗評估結果顯示, 本研究所提出之派工方法為多項績效指標之整體性較佳解。 意即, 比傳統之派工法則, 較能兼顧多屬性之產線特性與排程目標。
With the development of semiconductor advanced technologies (0.15um à 0.13um à 90nm) is rising and competing drastically, the wafer test plays a more significantly important role in providing the promptest yield feedback for quick process improvement. Nevertheless, the shop floor of wafer test is getting even complicated than before due to the increasing change over rate, non-linear wafer arrival and urgent orders preemption behavior. Furthermore, the foundry wafer test is a heterogeneous production with different products of cycle time and non-identical testers in large variance. The shop floor condition including WIP pool, tester status and work order priority keeps changing all the time. In order to operate such kind of production line to simultaneously fulfill the multiple objectives such like maximum CLIP (confirmed line item performance) for normal lots, 100% CLIP for urgent lots, minimum change-over rate and shortest cycle time, a reactive dispatching approach, which is expected to perform a real-time solution no matter how/what the shop floor would change dynamically, is proposed. The dynamic approach is mainly triggered by two kinds of major events, one is when an urgent lot come in, and the other is when a tester is idle. In addition, through a two-phase dispatching algorithm, lot ranking and lot assignment methods, prioritized WIP lots and an appropriate lot assignment are suggested. The experimental results reveal that the better performance measure is obtained under the entire consideration of multiple objectives, which are the wafer test operations desire to achieve.
ABSTRACT 1
ACKNOWLEDGE 2
CONTENT 3
FIGURE LIST 5
TABLE LIST 6
1.0 INTRODUCTION 7
1.1 Background 7
1.2 Objectives 8
1.3 Scope 9
1.4 Research step 10
2.0 WAFER TEST OPERATION AND PROBLEM ANALYSIS 12
2.1 Semiconductor testing introduction 12
2.2 Wafer test operation introduction 14
2.2.1 Equipments of wafer probing 14
2.2.2 Categories and flows of wafer testing 18
2.3 Role of dispatching for test operations 20
2.4 Problem analysis 22
2.4.1 Dispatching characteristics 22
2.4.2 Multiple objectives of wafer test 25
2.4.3 Summary of core problems 27
3.0 LITERATURE REVIEW 28
3.1 Semiconductor scheduling related literatures 28
3.2 Multi-attributes/criteria related literatures of semiconductor scheduling 30
4.0 A DYNAMIC DISPATCHING APPROACH PROPOSITION 32
4.1 Architecture of a dynamic dispatching 32
4.2 I/O Analysis 33
4.2.1 Input 34
4.2.2 Output 39
4.3 Dynamic circumstances 39
4.4 Event driven approaches 40
4.5 Two-phase dispatching approaches 41
4.5.1 Lot ranking method 41
4.5.2 Lot assignment method 48
5.0 SYSTEM PERFORMANCE EVALUATION 58
5.1 Wafer test flow assumption for simulation 58
5.2 Problems description 58
5.3 Boundary 59
5.4 Rules of DDA lot ranking 59
5.5 Input factors and levels 60
5.6 Performance indices of evaluation 61
5.7 Hypotheses of the model 61
5.8 Analysis of simulation results 62
5.9 Conclusions of simulation 65
6.0 CONCLUSION AND RECOMMENDATION 66
6.1 Conclusion 66
6.2 Recommendation 66
REFERENCE 68
1. Chen, H. N., “Optimizing multi-objective daily production plans for complex manufacturing facilities,” PhD. Thesis, Arizona State University, 2001.
2. Dabbas, R. M., Chen, H. N., Fowler, J. W., and Shunk, D., “A combined dispatching criteria approach to scheduling semiconductor manufacturing systems,“ Computers and Industrial Engineering, Vol. 39, pp. 307-324, 2001.
3. Deng, F. Y., “Analysis of shop floor operations scheduling for wafer probe area,” MS. Thesis, National Tsing Hua University, 1998.
4. Derringer, G., and Suich, R., “Simultaneous optimization of several response variables,” Journal of quality technology, Vol. 12, No. 4, pp. 214-219, October 1980.
5. Grabot, B. and Geneste, L., “Dispatching rules in scheduling: a fuzzy approach,” International Journal of Production Research, Vol. 32, No. 4, pp. 903-915, 1994.
6. Kuo, P. C., “Simulation analysis of multi-attribute product scheduling problem in wafer probe area,” MS. Thesis, National Tsing Hua University, 2002.
7. Lee, C. Y., Martin-Vega, L. A., Uzsoy, R. and Hinchman, J., “Implementation of a decision support system for scheduling semiconductor test operations”, Journal of Electronics Manufacturing, Vol. 3, No. 3, pp. 121-131, 1993.
8. Li, W. T., “A study of tester scheduling for logic IC final testing,” MS. Thesis, National Tsing Hua University, 2000.
9. Lin, T. C., “A short-term production scheduling for logical IC final testing factory,” MS. Thesis, National Tsing Hua University, 1997.
10. Ovacik, I. M. and Uzsoy, R., “Worst-case error bounds for parallel machine scheduling problems with bounded sequence-dependent setup times,” Operations Research Letters, Vol. 14, No. 5, pp. 251-256, 1993.
11. Perry, C. N. and Uzsoy, R., “Reactive scheduling of a semiconductor testing facility”, Fifteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium, pp. 191-194, 1993.
12. Ramesh, R. and Cary, J. M., “An efficient approach to stochastic jobshop scheduling: Algorithms and empirical investigations,” Computers and Industrial Engineering, Vol. 18, No. 2, pp. 181-190, 1990.
13. Sivakumar, A. I., “Multiobjective dynamic scheduling using discrete event simulation,” International Journal of Computer Integrated Manufacturing, Vol.14, No.2, pp. 154-167, 2001.
14. Uzsoy, R., Church, L. K., Ovacik, I. M. and Hinchman, J., “Performance evaluation of dispatching rules for semiconductor testing operations,” Journal of Electronics Manufacturing, Vol. 3, pp. 95-105, 1993.
15. Uzsoy, R., Lee, C. Y. and Martin-Vega, L. A., “Scheduling semiconductor test operations: Minimizing maximum lateness and number of tardy jobs on a single machine”, Naval Research Logistics, Vol.39, pp. 369-388, 1992.
16. Uzsoy, R., Lee, C. Y., and Martin-Vega, L. A., “A review of production planning and scheduling models in the semiconductor industry, Part I: System characteristics, performance evaluation and production planning,” IIE Transactions, Vol. 24, No. 4, pp. 47-60, 1992.
17. Uzsoy, R., Martin-Vega, L. A., Lee, C. Y. and Leonard, P. A., “Production scheduling algorithm for a semiconductor test facility”, IEEE transactions on semiconductor manufacturing, Vol.4, No.4, pp. 270-280, 1991.
18. Uzsoy. R., Church, L. K., Ovacik, I. M., and Hinchman, J., “Dispatching rules for semiconductor testing operations: a computational study,” IEEE/CHMT Int. Elec. Manufacturing Technology Symposium, pp. 272-276, 1992.
19. Wroblewski, K. and Krawczynski, R., “Priority rules in production flow control,” Material Flow, Vol. 2, pp. 167-177, 1985.
20. Yang, J. and Chang, T. S., “Multiobjective scheduling for IC sort and test with a simulation testbed”, IEEE transactions on semiconductor manufacturing, Vol.11, No.2, pp. 304-315, 1998.
21. Yang, J., Chang, T. S., Chang, H. and Kao, J., “Optimization-based dynamic scheduling and its testbed for IC sort and test”, Proceedings of the 35th IEEE Conference on Decision and Control, Vol.3, pp. 2759-2762, 1996.
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1. 林宗達〈2001年〉,「美國發展國家飛彈防禦計劃研析」,中華戰略學刊,夏季刊,民國90年7月,頁113-142。
2. 郭獻忠〈1991年〉,「波灣戰後美國新全球戰略之構想」,美國月刊,第六卷第十二期,民國80年12月,頁27-37。
3. 楊文鎮〈1999年〉,「柯索夫戰事之探討與體認」,國防雜誌,第十五卷第三期,民國88年9月,頁95-115。
4. 林文程〈1993年〉,「後冷戰時期美國的國家安全政策」,美國月刊,第八卷第六期,民國82年6月,頁4-14。
5. 畢英賢〈1993年〉,「美俄關係的發展方向」,美國月刊,第八卷第三期,民國82年3月,頁4-16。
6. 鈕先鍾〈1991年〉,「蘇聯變局後的美國戰略」,美國月刊,第六卷第十二期,民國80年12月,頁4-10。
7. 衛嘉定〈1993年〉,「美國總統科林頓之總體外交新架構」,問題與研究,第三十二卷第五期,民國82年5月,頁24-31。
8. 張惠玲〈2000年〉,「歐盟『共同外交暨安全政策』之運作理論與發展」,問題與研究,第三十九卷第十一期,民國89年11月,頁49-70。
9. 湯紹成〈2000年〉,「後冷戰時期北大西洋公約組織角色與功能的轉變」,問題與研究,第三十九卷第一期,民國89年1月,頁67-78。
10. 翁明賢〈1994年〉,「後冷戰時期北約與歐洲安全關係」,美歐月刊,第九卷第八期,民國83年3 月,頁4-18。
11. 沈玄池〈2000年〉,「歐洲聯盟共同外交暨安全政策體制與運作方式改革之研究」,美歐季刊,第三十九期,秋季號,民國89年9月,頁263-304。
12. 楊永明〈1997年〉,「美國亞太安全戰略之理論分析」,美歐季刊,民國86年,冬季號,www.cc.ntu.edu.tw/-yang/paper-10.htm
13. 謝勝義〈1997年〉,「歐洲安全與俄羅斯的角色」,俄情雜誌,第六卷第二期,民國86年4月,頁1-5。
14. 劉書彬〈2000年〉,「歐洲聯盟東擴的課題與影響─以波蘭、捷克、匈牙利申請加入歐盟為例」,中山人文社會科學期刊,第八卷第一期,民國89年6月,頁209-236。
15. 李大中〈1996年〉,「北約之轉型:德國與大西洋兩岸秩序的重建」,問題與研究,第三十五第三期,民國85年3月,頁65-80。