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研究生:劉俊濱
論文名稱:半導體晶圓廠控片規劃研究
論文名稱(外文):Control wafer planning for semiconductor wafer fabrication
指導教授:洪一峰洪一峰引用關係
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工業工程與工程管理學系
學門:工程學門
學類:工業工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:42
中文關鍵詞:控片降級線性規劃模式半導體晶圓廠
相關次數:
  • 被引用被引用:7
  • 點閱點閱:1537
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  • 下載下載:0
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半導體工業為資本密集產業,隨著需求及應用的增加,各晶圓廠的產能皆大幅的提昇,隨著晶圓直徑的增加,如何降低製造成本成為各廠間首要面臨的問題。晶圓的良率直接地影響著製造的成本,而控片則是晶圓廠間用來控制及提升晶圓良率的方法,晶圓的製造過程中,藉由控片來監控正常晶圓的品質與量測製程中生產機台的參數,控片雖非正常產品,但卻為生產正常晶圓時不可缺乏的。
在控片的使用上,一旦缺乏控片則將使機台無法監測,造成生產線的停擺,使的正常晶圓無法順利生產,故為了避免控片的缺乏造成產能損失,一般晶圓廠在現場皆放置了大量的控片,大量的控片卻也造成了成本的浪費與資金的積壓。因此,本文考量控片的使用流程與降級特性,在控片不缺乏的前提下,發展一控片使用之規劃。
本論文針對控片的使用情形提出線性規劃模型,根據各作業對控片的需求,發展一考量時程參數之控片規劃模式,利用網路問題之特性以線性規劃軟體迅速求出在滿足生產需求下最低控片使用量之計畫。

Semiconductor industry is capital-intensive industry. Due to increasing demand, many semiconductor companies raise their capacity substantially. How to reduce manufacturing cost becomes an important issue. The yield of wafer influences manufacturing cost directly. The use of control wafer is to control the wafer quality. For wafer manufacturing process, control wafer are used to maintain the quality of production wafer and monitor the environment of production equipments. Control wafers are not regular wafers for sale, but they are indispensable for wafers fabrication.
Lack of control wafers will stop production line. In order to avoid this problem, most wafer factories keep a large number of control wafers inventory. A large number of control wafers imply a huge amount of inventory costs. Considering control wafer usage and downgrade rule, this study develop a control wafers production planning system to schedule the usage of control wafers under the assumption that control wafer can not be short.
This study develops a linear programming model, based on the demand of manufacturing operation. By using this formulation, hopefully we can quickly obtain a plan, which minimize the usage of new control wafer.

第1章 緒論 1
1.1研究背景 1
1.2控擋片簡介 2
1.2.1控片的四個使用流程 2
1.2.2控片降級法則 5
1.2.3控片的使用時機 7
1.3研究動機 8
1.4研究目的 8
1.5研究方法 8
1.6本文架構 9
第2章 文獻探討 10
2.1控擋片在製品存貨管理 10
2.1.1在製品存貨對生產活動之影響 10
2.1.2控擋片存貨管理機制 10
2.2控擋片降級法則 15
2.2.1推式及拉式生產系統 15
第3章 研究方法與程序 18
3.1問題假設與名詞定義 18
3.1.1問題假設 18
3.1.2時程參數 18
3.2應用動態生產函數描述半導體控片生產流程 19
3.3控片管理線性規劃模型 23
第4章 運算結果與分析 31
4.1範例說明 31
4.2評估準則 36
4.3運算結果與分析 36
第五章 結論與未來展望 40
參考文獻 41

1.Chen, H.C. and Lee, C.E. (2000), “Downgrading management for control and dummy wafers”, Journal of the Chinese Institute of Industrial Engineers, Vol. 17, No. 4, pp. 437-449.
2.Chu, Y. F. (1998), The Inventory Management Model for Control and Dummy Wafers, Master Thesis , National Chiao Tung University, Hsin-chu Taiwan , R.O.C.
3.Conway, R., Maxwell, W., McClain, J. O., and Thomas, L. J. (1988), “The role of work-in-process inventory in serial production lines”, Operation Research, Vol. 36, No. 2, pp. 229-241.
4.CPLEX(1999), Reference Manual, ILOG CPLEX 6.5.
5.Hung, Y. F. (1991), Corporate-Level Production Planning with Simulation Feedback Of Parameters, Ph.D. Dissertation, College of Engineering, University of California at Berkeley, CA.
6.Johri, P.K. (1992), “Optimal partitions for shop floor control in semiconductor Wafer fabrication”, European Journal of Operational Research, Vol. 59, No. 2, pp. 294-297.
7.Leachman, R. C. and Carmon, T. F. (1992), “On capacity modeling for production planning with alternative machine types”, IEE Transactions, Vol. 24, No. 4, pp. 62-72.
8.Leachman, R. C. (1993), Modeling techniques for Automated Production Planning in the Semiconductor Industy, Optimization in Industry, Cirani, T. A. and Leachman, R. C. (Editors), John Wiley and Sons, Ltd, England, pp. 1-30.
9.Lu, S. C. H., Ramaswamy, D., and Kumar, P.R. (1994), “Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants”,
Semiconductor Manufacturing, IEEE Transactions, Vol. 73, No. 8, pp. 374 —388.
10.Meyersdorf, D., Yang, T. (1997), Cycle Time Reduction for Semiconductor Wafer Fabrication Facilities, 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, pp. 418 —423.
11.Meyersdorf, D., Foster, B., Padillo, M., Brenner, R. (1998), Simulation of Test Wafer Consumption in a Semiconductor Facility Foster, 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, pp. 298 —302.
12.Uzsoy, R., Lee, C.Y., and Martin-Vega, L. A. (1992), “A review of production planning and scheduling models in the semiconductor industry partⅠ: system characteristics, performance evaluation and production planning”, IEE Transactions : Industrial Engineering Research and Development , Vol. 24, pp. 47-60.
13.Watanabe, A., Kobayashi, T., Egi, T., and Yoshida, T. (1999),Continuous and Independent Monitor Wafer Reduction in DRAM Fab, 1999 IEEE International Symposium Semiconductor Manufacturing Conference Proceedings, pp. 303 —306.
14.Wong, C.Y. and Hood, S. J. (1994 ), Impact of Process Monitoring in Semiconductor Manufacturing, 1994 IEMT Symposium Electronics Manufacturing Technology Symposium, Low-Cost Manufacturing Technologies for Tomorrow's Global Economy .Proceedings 1994 IEMT Symposium., Sixteenth IEEE/CPMT International, Vol. 1, pp. 221 —225.
15.施欣玫(1996)半導體製造業訂單管理與生產計畫演算法,清華大學工業工程碩士論文
16.林永龍(1999)晶圓製造廠爐管區之控擋片存量控制模式設計,交通大學工業工程碩士論文
17.王明宏(1998)控片存貨水準之設定,交通大學工業工程碩士論文

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