臺灣博碩士論文加值系統

摘要
隨著光纖通訊的蓬勃發展，許多前所未見的挑戰逐漸浮現。肇因於光纖對位精密度要求高、不易大量生產緣故，如何生產一具成本優勢的光纖元件遂成重要目標。將光纖與元件整合於矽基材的被動對位技術或許提供了一個可靠的節決方案，此類型的整合技術包含了蝕刻V型槽與覆晶凸塊製程。V型槽和覆晶凸塊能確保被動對位的高水平與垂直精確度。本研究所設計的矽基材乃利用IC製程中的光罩和氧化薄膜進行。
肇因於容易達成光纖被動對位，自1990年開始，即有許多關於製造與設計的研究進行。然本研究著重於不同部分，本研究著重於整體結構的可靠度分析與覆晶凸塊外型預測。因此本研究將分別利用有限元素法分析結構在熱循環測試之下的力學行為。與Surface Evovler 預測錫球凸塊的幾何外型，達到準確對位之目標。因此，本研究的主要目的乃是要利用電腦輔助軟體簡化設計光學構裝的工作程序。
關鍵字：被動對位、覆晶凸塊、有限元素法、可靠度、光學構裝

Abstract
With the development of optical fiber communication industry, the challenges for producing more cost-effective fiber-optic modules are mainly due to high Electro-optic performance, low volume production, and high reliability requirements. Fiber-in-board technology offers a full solution for those requirements. The technology is based on silicon micro-optical bench with etched V-grooves and flip-chip solder bonding. V-grooves and flip-chip solder bump designed for optical passive alignment provides a precise passive alignment packaging method. High accuracy in horizontal and vertical alignment of optical chip was attained. Silicon micro-optical bench substrates were manufactured together on silicon wafer via photolithography and thin-film processing.
Based on this concept, lots of researches investigate bumping technology and manufacturing process since 1990.This research will focus on different issue. The reliability analysis of optical passive alignment structures and the solder joint design, such as solder geometry shape control, is the main issue in this research. This research will use finite element method to analyze the mechanics behavior of testing vehicle under thermal cycling condition. In order to provide good reliable structure, this research will also use Surface Evovler to predict geometry of solder bump. The main goal of this research is using computer-aided software to design optical packaging.
Keyword : Passive Alignment, Flip Chip Solder Bump, Finite Element Method, Reliability, Optical Packaging

目錄
摘要……………………………………………………………..I
Abstract………………………………………………………...II
目錄………………………………………………………….. III
圖目錄………...……………………………………………...VII
表目錄……………………………………………………...VIIII
第一章 緒論
1.1 研究動機…………………………………………………….. 1
1.2 研究目的…………………………………………………….. 3
1.3 光纖對位之問題…………………………………………….. 4
1.3-1 主動對準…………………………………………….. 5
1.3-2 被動對準…………………………………………….. 5
1.4 光電元件構裝概況…………………………………………. 6
1.5 研究範疇…………………………………………………….. 7
第二章 文獻回顧
2.1 矽的非等向性蝕刻…………………………………………. 8
2.2 覆晶接合技術………………………………………………. 8
2.3 Surface Evolver的應用歷史………………………………... 10
2.4 覆晶結構可靠度……………………………………………. 11
第三章 理論分析
3.1 光纖對位的重要性…………………………………………. 12
3.2 光纖的內部損失……………………………………………. 13
3.2-1 照射損失…………………………………………….. 13
3.2-2 吸收損失…………………………………………….. 14
3.3 光纖的外部損失……………………………………………. 16
3.3-1 照明損失…………………………………………….. 17
3.3-2 數值孔鏡損失……………………………………….. 18
3.3-3 光纖輸出端耦合損失……………………………… 19
3.3-4 反射損失…………………………………………….. 20
3.4 二光纖對接損失……………………………………………. 21
3.4-1 橫向未對準………………………………………….. 21
3.4-2 角向未對準………………………………………….. 23
3.4-3 端點分離未對準…………………………………….. 24
3.5 Surface Evolver之理論分析………………………………... 26
3.6 可靠度估算準則……………………………………………. 28
3.6-1 Pao所提出之Coffin Manson經驗式………………... 28
3.6-2 Hong所提出之Coffin Manson經驗式……………… 29
3.7 有限元素法…………………………………………………. 30
3.7-1 應力與應變關係…………………………………….. 30
3.7-2 降伏準則…………………………………………….. 31
3.7-2 應變硬化法則……………………………………….. 32
第四章 有限元素模型
4.1 結構有限元素分析…………………………………………. 34
4.1-1 材料參數設定……………………………………….. 34
4.1-2 邊界條件設定……………………………………….. 36
4.1-3 熱循環條件設定…………………………………….. 37
4.2 測試載具結構與散熱分析分析……………………………. 39
4.2-1 材料參數設定……………………………………….. 40
4.2-2 邊界條件設定………………………………………..
第五章 有限元素法之結果
5.2 熱循環下光纖端面之位移偏量……………………………. 44
5.1-1 X方向偏移量………………………………………... 44
5.1-2 Y方向偏移量………………………………………... 49
5.1-3 Z方向偏移量………………………………………... 54
5.1-4 結果與討論………………………………………….. 60
5.2 覆晶凸塊之可靠度…………………………………………. 64
5.3 測試載具熱傳分析結果……………………………………. 68
5.3-1 測試載具結構裸露之熱傳分析…………………….. 68
5.3-2 僅PCB與外界接觸之熱傳分析……………………. 70
第六章 實驗設計及進行步驟
6.1 實驗流程……………………………………………………. 73
6.1-1 高溫氧化爐管……………………………………….. 74
6.1-2 光阻微影製程系統………………………………….. 75
6.1-3 濕蝕刻……………………………………………….. 76
6.1-4 金屬濺鍍…………………………………………….. 76
6.2 Surface Evolver分析………………………………………... 77
6.3 V型槽之設計與製造……………………………………….. 79
6.4 結果與討論…………………………………………………. 81
第七章 結論與未來展望
參考文獻 86

參考文獻
1. J C. Palais, “Fiber Optic Communications”, McGraw-Hill, Inc., chandler,2000
2. 吳曜東, “光纖原理與應用”, 全華書局 , 民國86年（1997）
3. 蕭宏霖.“量測原理”,捷耀科技訓練教材,民國90年（2001）
4. D. B Lee, “Anisotropic Etching of Silicon”, J. App. Phy, pp.4569-4573, 1969.
5. E. Bassous, “Fabrication of Novel Three-dimensional micro Structure by the anisotropic etching of (100) and (110) silicon ”, IEEE transaction on electrons device, pp.1178 -1193,1978.
6. L. S. Goldmann, “Geometric Optimization of Controlled Collapse Interconnection”, IBM Journal of Research and Development, Vol. 120, pp.175-178, May 1969.
7. L. F. Miller, “Controlled Collapse Reflow chip Join”, IBM Journal of Research and Development, Vol.120, pp.239-250, May 1969.
8. M. J. Wale, “Self-aligned Flip Chip Assembly of Proton Device with Electrical and Optical Connection”, Electronic Components and Technology Conference, IEEE Trans on Comp, Vol.13, NO.4, pp.780-786, 1990
9. Y. C. Lee, “Studies on solder self-alignment ”. IEEE. LEOS '94 Conference Proceedings, Vol.1, pp.73 -74, 1994
10. K. A. Cooper, R. Yang, J. S. Mottet and G. Lecarpentier(Karl Suss & Lucent), “Flip chip Equipment for High End Electro-Optical Modules”, Electronic Components & Technology Conference, . 48th IEEE, pp.176 -180, 1998
11. M. Itoh, J. Sasaki and A. Uda, “Passive Alignment Packaging on Si Optical Bench Using AuSn Solder Bumps”, IEEE LEOS '97 10th Annual Meeting. Conference Proceedings, IEEE Vol. 2 , pp. 126 -127, 1996.
12. M. Itoh and J. Sasaki, “Use AuSn Solder in Three-dimensional Passive Aligned Packaging of LD/PD Arrays on Si Optical Benches ”, Proc of 46th ECTC ,Vol. 2,pp.1-7, 1996
13. Brakke, “Surface Evolver Manual, Version 2.01”, 1992.
14. L. M. Racz and J. Szekely, “Determination of Equilibrium Shapes and Optimal Volume Of Solder Droplets in the Assembly of Surface Mounted Integrated Circuits” ,ISIJ International, Vol. 33, pp.336-342. 1993
15. P. K. Bhatti, K. Gschwend, A. Y. Kwang and A. R. Syed, “ Three-Dimensional Creep Analysis of Solder Joints in Surface Mount Devices”, Transactions of the ASME, Vol. 117, pp.20-24. , 1995
16. K. N. Chiang, W. L. Chen, “Electronic Packaging Reflow Shape Prediction for the Solder Mask Defined Ball Grid Array”, ASME Transaction Journal of Electronic Packaging. Vol. 120, pp. 175-178, June 1998.
17. W.H. Chen, K. N. Chiang, and S. R. Lin, “Prediction of Liquid Formation for Solder and Non-Solder Mask Defined Array Packages”, ASME Journal of Electronic Packaging , Vol124, pp.37-44, March 2002
18. S. Liu, J. Wang, and Z. F. Qian,“Several Reliability Related Issues for Flip-Chip Packaging”, Solid-State and Interated Circuit Technology, 5th International conference, pp.543-545, 1998
19. D. Robert and B. Kingshuk,“Fatigue Analysis of Flip Chip Assemblies Using Thermal Stress Simulations and a Coffin-Manson Relation”, Electronic Components and Technology Conference, 1991.Proceedings, 41th,pp.797-805, 1991.
20. B. M. Romenesko,“Ball Grid Array and Flip Chip Technologies : Their Histories and Prospects”, The Internation Journal of Microcircuits and Electronic and Packaging , Vol.19, NO.1, pp.64-74 ,1996
21. P. Elenius,“Flip Chip Bumping for IC Packing Contractors“,Flip Chip Technologies, 1998
22. Z. Johnson, “Implementation of and Extensions to Darveaux’s Approach to Finite-Element Simulation of BGA Solder Joint Reliability”, Electronic Components and Technology Conference, IEEE, pp. 1190 —1195,1999.
23. Z. Qian and S. Liu, “On the Life Prediction and Accelerated Testing of Solder Joints“, EEP-vol. 24, Thermo-Mechanical Characterization of Evolving Packaging Material and Structure, ASME, pp. 1-12,1988
24. J. P. Clech,“ BGA, Flip-Chip and CSP Solder Joint Reliability: of the Importance of Model Validation“, InterPack, 1999
25. 張維群,“光纖通訊” ,高立出版社,民國89年(2000)
26. H. Zanger and C. Zanger,“Fiber Optics Communication and Other Application“, Macmillan Publishing Co, 1991
27. H. B. Killen ,“Fiber Optics Communication”, Prentice Hall ,1991
28. 龔純瑩, ”光纖連接技術簡介”, 光學工程47期, pp30-36,民國83年(1994)
29. L. F. Coffin, "A Study of Ef fects of Cyclic Thermal Stresses on a Ductile Metal", Transactions of the Amer i can Society of Mechanical Engineers, 76, 931,950, 1954.
30. S. S Manson, "Behavior of Materials under Conditions of Thermal Stress", National Advisory Commission on Aeronautics, Report 1170, Cleveland: Lewis Flight Propulsion Laboratory, 1954
31. Bellcore TA-NWT-009083
32. J. H. Lau and Yi-Hsin Pao, “ Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies” , McGraw-Hill, pp48-136 , 1997
33. B. Z. Hong, T.D. Tuan, and L. Burrell, “Anisothermal fatigue Analysis of Solder Joint in a Convective CBGA Package Under Power Cycling,” EEP-Vol.17, Sensing, Modeling and Simulation in Emerging Electronic Packaging, ASME, pp.39-46, 1996
34. L. Li and B. H. Yeung,“wafer Level and Flip Chip Design Through Solder Prediction model and Validation”, IEEE Transactions on Components and Packing Technologies , Vol.24, NO.4, pp.650-654, 2001
35. B. H. Yeung, T.Y. Lee,“ Evaluation and Optimization of Package Processing, Design, and Reliability through Solder Joint Profile Prediction”, IEEE Transactions on Components and Technology Conference,pp.925-930,2001
36. Ellison, G. N., “Thermal Computations for Electronic Equipment”, Van Nostrand Reinhole Company, New York, 1989