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研究生:余明道
研究生(外文):Ming-Dow Yu
論文名稱:應用相關時序差異的時鐘樹緩衝器尺吋設計
論文名稱(外文):Clock Tree Buffer Sizing with Applying Connective Skew
指導教授:張世杰張世杰引用關係
指導教授(外文):Shih-Chieh Chang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:38
中文關鍵詞:時鐘樹時序差異緩衝器尺吋設計
外文關鍵詞:clock treeclock skewbuffer sizing
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在現今的晶片設計中,時鐘的設計扮演了很重要的角色。在時鐘網路的設計中,目前最普遍採用在現今晶片設計的是緩衝器式時鐘樹。在本篇論文中,因為,傳統上,時序差異的定義太過於悲觀,所以,我們提出了一個新的時序差異的概念,相關的時序差異。此外,我們提出了兩種緩衝器尺吋設計的演算法來應用相關的時序差異,分別是基因演算法和梯度搜尋演算法。實驗結果顯示,梯度搜尋演算法可以快速找出一組不錯的解,很適合當作基因演算法的初始解,以增快基因演算法最佳化的速度。最後,我們將提出之相關時序差異的概念和兩種緩衝器尺吋設計的演算法加入現有的設計流程中。而我們最佳化的目標是將現有設計工具產生之實際電路的時鐘樹加入相關時序差異的概念,並且利用緩衝器尺吋設計演算法來作時鐘樹功率消耗最佳化。實驗結果顯示,五種實際的電路採用相關時序差異後經由最佳化,平均可以降低約百分之十的時鐘樹功率消耗。

Clock designs play an important role in modern VLSI designs. Among clock network designs, the buffered clock tree architecture is the most popular clock network design adopted in modern VLSI designs. In this thesis, we have proposed a new skew concept, connective skew. Since, the traditional clock skew definition is too pessimistic. Moreover, we have proposed two buffer sizing algorithm, genetic algorithm and gradient search algorithm with applying connective skew. The experimental results show that gradient search algorithm can be a good initial solution for genetic algorithm. Finally, we have incorporated our algorithms with the current cell-based design flow. Our optimization goal is to apply the connective skew to clock tree such that the power consumption of the circuit will be minimized under the same skew constraint. From experimental results, applying connective skew to clock tree buffer sizing program can achieve about 10% of power minimization than applying traditional clock skew. In summary, we can reduce the power consumption of real circuits’ clock tree by integrating our proposed clock tree buffer sizing approach into current cell-based design flow.

ABSTRACT I
CONTENTS II
LIST OF FIGURES III
LIST OF TABLES IV
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 PREVIOUS WORK 5
2.1. CLOCK SKEW MINIMIZATION 5
2.2. CLOCK SKEW UTILIZATION 6
CHAPTER 3 PROPOSED APPROACH 8
3.1 CONNECTIVE SKEW 8
3.2 CLOCK TREE BUFFER SIZING ALGORITHM 12
3.2.1 Genetic Algorithm 12
3.2.2 Gradient Search Algorithm 15
3.3 CLOCK TREE BUFFER SIZING FOR POWER OPTIMIZATION 17
3.3.1 Clock Tree Buffer Sizing Flow 17
3.3.2 Delay and Clock Power Calculation 20
CHAPTER 4 EXPERIMENTAL RESULTS 24
4.1 BENCHMARK PROFILES 24
4.2 CONNECTIVE SKEW VS. CLOCK SKEW 25
4.3 GRADIENT SEARCH ALGORITHM VS. GENETIC ALGORITHM 28
4.4 GRADIENT SEARCH ALGORITHM + GENETIC ALGORITHM VS. GENETIC ALGORITHM 30
CHAPTER 5 CONCLUSIONS 33
BENCHMARK STUDY 35
A.1 MEAN FILTER 35
A.2 GRAVITY CENTER CALCULATOR 35
A.3 32/64 BIT MAC (MULTIPLIER AND ACCUMULATOR) 35
A.4 H.26L MOTION ESTIMATOR 36
BIBLIOGRAPHY 37

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[13] E.G. Friedman, “Clock Distribution Networks in Synchronous Digital Integrated Circuits,” Proc of the IEEE, Volume 89, NO. 5, 2001.

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