跳到主要內容

臺灣博碩士論文加值系統

(3.239.4.127) 您好!臺灣時間:2022/08/16 02:46
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:賴良維
研究生(外文):Andy Liang-Wei Lai
論文名稱:具有高範圍輸出電壓及可減少內在像素固定雜訊之新型對數極式互補金氧半導體影像感測器
論文名稱(外文):A Novel Logarithmic Response CMOS Image Sensor with High Output Voltage Swing and In-pixel Fixed Pattern Noise Reduction
指導教授:金雅琴
指導教授(外文):Ya-Chin King
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:75
中文關鍵詞:影像感測器光二極體
外文關鍵詞:CMOS image sensorphotodiodeCMOS APSlateral PNP
相關次數:
  • 被引用被引用:1
  • 點閱點閱:402
  • 評分評分:
  • 下載下載:109
  • 收藏至我的研究室書目清單書目收藏:1
互補式金氧半導體影像感測器已廣泛地用在數個應用產品上,如動態攝影機、數位相機、行動電話、個人數位助理器和筆記型電腦,且它的需求量也正逐年上升中,在系統單晶片整合成功後,有可能取代電荷耦合元件現今在各種產品的應用。
對數極式影像感測器的動態範圍較一般線性式影像感測器的為高,對數極式影像感測器的動態範圍約為120dB,偵測光的範圍可從滿月的夜晚到直接處於正午大太陽底下,但其低範圍輸出電壓及較大的固定雜訊卻是其缺點,而線性式影像感測器其動態範圍約為60dB,可偵測光的範圍小。
在本篇論文中,我們針對台積電零點二五微米製程技術提出了一種新型的對數極式影像感測器,其輸出電壓範圍為原始結構的數倍,藉以符合一般類比/數位轉換器輸入電壓範圍的需求(至少要1伏特),並且能夠大大減低內在像素的固定雜訊錯誤,並且經由放大訊號,將使其影像的對比度大大的提高。
另外,我們提出一種應用於內部像素的相關雙重取樣開關電路,用於對數極式影像感測器,能夠消除內在像素的固定雜訊。
最後,我們將兩種提出來的技術合而為一,發現能大大的減低固定雜訊 (約從27%的Vsat RMS[飽和電壓之均方根值,通常為全部訊號電壓值]減低到2.46%Vsat RMS ),並且能提供約1.3伏特的輸出電壓給後段的類比/數位轉換器。

CMOS image sensor has been widely used in various applications, such as video camera, digital camera, mobile phone, PDA, and laptop. The demand of CMOS image sensor is expected to rise rapidly in the next few years. As high-level integrated chips, SoC (system-on-chip), CMOS image sensor might replace CCD to become the mainstream product as the first semiconductor imaging choice.
The conventional logarithmic-mode CMOS image sensor demonstrates wide dynamic range comparing to the linear-mode CMOS image sensor. But its low output voltage swing and large FPN (Fixed Pattern Noise) make it less attractive.
A novel logarithmic response CMOS image sensor for 0.25μm CMOS technology is proposed. The new cell has a much higher output voltage swing than a conventional structure, making it more compatible with the A/D converter. In addition, to reduce the FPN in logarithmic mode CMOS APS (Active Pixel Sensor), a new cell with in-pixel CDS (Correlated Double Sampling) control, is proposed. The FPN (Fixed Pattern Noise) of this new logarithmic-mode image sensor can be greatly reduced from 54mV to 10mV. Furthermore, the output signal variation of the log-mode CMOS APS combined with lateral PNP and an in-pixel CDS control transistor due to FPN can be greatly reduced from 27% of Vsat RMS (total signal voltage range) to 2.46% of Vsat RMS.

Abstract ………………………………………………………i
Acknowledgements ………………………………………… iii
List of Contents ………………………………………… iv
Chapter One Introduction ………………………………1
1.1 Introduction to CMOS image sensor …………1
1.2 Challenges and solutions ………………………1
1.3 Organizations …………………………………………3
Chapter Two CMOS Image Sensor Review ………………6
2.1 Charge Coupled Device (CCD) …………………6
2.2 CMOS Based Image Sensor ………………………7
2.2.1 CMOS Passive Pixel Sensor (PPS) ………8
2.2.2 CMOS Linear Mode Active Pixel Sensor (APS) …9
2.2.3 CMOS Photogate APS …………………………… 10
2.3 Pinned Photodiode APS (PPAPS) ……………………… 11
2.4 Thin Film on ASIC APS (TFAAPS) ………………………11
2.5 CMOS Logarithmic Mode Active Pixel Sensor …………12
2.6 The Scaling Perspectives of CMOS APS ………………13
2.7 Image Quality Figures …………………………………14
2.7.1 Dynamic Range (DR) ………………………………14
Chapter Three Figure of Merit; Noise in an Imager,
and Experimental Preparation …………………………………32
3.1 Sensitivity ………………………………………………32
3.2 Noise of CMOS image sensor …………………………33
3.2.1 Thermal noise ……………………………………33
3.2.2 Dark current ………………………………………33
3.2.3 Fixed Pattern Noise (FPN) ……………………35
3.3 Experimental preparation …………………………… 35
3.3.1 The test structures and fabrication ………35
3.3.2 The test environment ……………………………36
Chapter Four A Novel Logarithmic Response CMOS Image Sensor with High OutputVoltageSwing ……………………..... 43
4.1 Pixel circuit design …………………………………43
4.2 Current amplification by lateral PNP implemented …43
4.3 Experimental results and discussions ………………45
Chapter Five A Novel Logarithmic Response CMOS Image Sensor
with Fixed Pattern Noise Reduction …………………… 61
5.1 New In-pixel CDS control circuit design ………… 61
Chapter Six Conclusion ………………………………………… 72
References …………………………………………………………… 74

[1] Chen Xu; Weiquan Zhang; Chan, M. “A Low Voltage Hybrid Bulk/SOI CMOS Active Pixel Image Sensor,” IEEE Electron Device Letters , Volume: 22 Issue: 5 , pp.248 ~250, May 2001.
[2] Dun-Nian Yaung; Shou-Gwo Wuu; Yean-Kuen Fang; Wang, C.S.; Chien-Hsien Tseng; Mon-Song Lian, “Nonsilicide Source/Drain Pixel For 0.25 um CMOS Image Sensor,” IEEE Electron Device Letters , Volume: 22 Issue: 2 , pp.71 ~73, Feb. 2001.
[3] Hon-Sum Philip Wong, “CMOS Image Sensors-Recent Advances and Device Scaling Considerations,” Electron Devices Meeting, 1997. Technical Digest., International, pp.201~204, 1997.
[4] N. Ricquier and B. Dierickx, “Pixel Structure with Logarithmic Response for Intelligent and Flexible Imager Architectures,” Microelectronic Engineering, Vol.19, pp.631~634, 1992.
[5] Kavadias, S.; Dierickx, B.; Scheffer, D.; Alaerts, A.; Uwaerts, D.; Bogaerts, J. “A Logarithmic Response CMOS Image Sensor with On-Chip Calibration,”
Solid-State Circuits, IEEE Journal of , Volume: 35 Issue: 8 , pp.1146~1152, Aug. 2000.
[6] Loose, M.; Meier, K.; Schemmel, J. “A Self-Calibrating Single-Chip CMOS Camera with Logarithmic Response,” Solid-State Circuits, IEEE Journal of , Volume: 36 Issue: 4, pp.586~596, April 2001.
[7] Richard S. Muller and Theodore I. Kamins, “Device Electronics for Integrated Circuits,” John Wiley & Sons, 1986.
[8] Tarek Lule, et. al. ,”Sensitivity of CMOS Based Imagers and Scaling Perspectives,” IEEE Trans. on Elect. Dev., vol.47, no. 11, p.2110, November 2000.
[9] Hi-Deok Lee and Jeong-Mo Hwang , ”Accurate Extraction of Reverse Leakage Current Components of Shallow Silicided p+-n Junction for Quarter- and Sub-Quarter-Micron MOSFET’s,” IEEE Trans. on Elect. Dev., vol.45, no. 8, p.1848, August 1998.
[10] A. ElGamal, “Image Sensors and Digital Cameras”, the lectures in Stanford University, 2001.
[11] Song Ye, et al., “A 1 V, 1.9 GHz Mixer Using a Lateral Bipolar Transistor in CMOS,” Low Power Electronics and Design, International Symposium, p.112, 2001.
[12] Duerden, G.D. et al., “The Development of Bipolar Log Domain Filters in a Standard CMOS Process,” ISCAS, vol.1, p.145, 2001.
[13] D. MacSweeney et al., “A SPICE Compatible Subcircuit Model for Lateral Bipolar Transistors in a CMOS Process,” IEEE Trans. on Elect. Dev., vol.45, no. 9, p.1978, 1998.
[14] Rudy Van De Plassche, “Integrated Analog-to-Digital and Digital-to-Analog Converters,” Kluwer Academic Publishers, 1994.
[15] Y. Ni, K. Matou, “A CMOS Log Image Sensor with on-chip FPN Compensation”, ESSCIRC'2001, 18-20 Sept. 2001 Villach, Austria, pp. 128-132.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top