臺灣博碩士論文加值系統

由最大gm外插法萃取 (gm-maximum extrapolation method) 臨界電壓值 (Vt) 會受到汲極串聯電阻增大的影響而產生誤差, 在本論文中我們證明在熱載子加速(hot carrier stress) 測試中若有電子陷在氮化矽間隙壁中(nitride spacer),其會影響由最大gm外插法來萃取臨界電壓值,而產生電洞被捕捉的錯誤判斷. 我們也推倒校正過後的公式來避免此一影響, 並由定電流萃取臨界電壓值法來驗證此公式的正確性.
氮化矽間隙壁底層氧化層 ( nitride spacer bottom oxide) 對熱載子破壞行為有著重要的影響, 然而其厚度如果太厚的話則會降低元件的電流導通能力, 氮化矽間隙壁底層氧化層厚度的最佳化設計會隨著複晶矽閘極 (polysilicon gate) 的結構的變化而不同, 在此論文中我們探討氮化矽間隙壁底層氧化層對熱載子破壞行為的關係與其厚度的最佳化設計. 我們發現隨著複晶矽閘極厚度的增加, 氮化矽間隙壁底層氧化層的厚度也需隨之變厚, 而其厚度的最佳化可由觀察早期最大基版電流 (substrate current) 情況下的熱載子加速測試的變化而得知, 在此論文中我們也詳細探討氮化矽間隙壁金氧半電晶體的熱載子退化行為與其相對應的物理模型.
在超薄閘極氧化層(ultra-thin gate oxide) 電晶體的低閘極電壓熱載子測試中(low gate hot carrier stress), 傳統被認知的電洞 (hole) 與中性電子(neutral electron) 的被抓取行為已經不復存在. 這是因為在超薄閘極氧化層電晶體的低閘極電壓熱載子測試中熱電洞已經發生直接穿隧效應 (direct tunneling) 而不再被陷在氧化層中. 取而代之的熱載子破壞行為是由介面陷阱狀態 (interfacial states) 來主導, 我們證明在超薄閘極氧化層電晶體中由低閘極電壓到最大基版電流的熱載子測試都是由介面陷阱狀態來主導元件的退化行為.
我們證明由熱載子測試中基版電流的變化來判斷熱載子導致的破壞種類已經不適用在超薄閘極氧化層電晶體中. 這是由於在超薄閘極氧化層電晶體中飽和模式下的元件特性也大幅受到熱載子破壞的影響, 而這種現象在早期的電晶體中是不會發生的. 這導因於當元件操作在飽和模式時, 熱載子的破壞只有少部分落在元件擠壓範圍內 (pinch off region), 而無法有效屏障住熱載子破壞對元件造成的影響.
在超薄閘極氧化層電晶體中, 中閘極電壓熱載子破壞 (medium gate voltage hot carrier damage) 是由熱載子碰撞導致離子解離 (impact ionization) 與電子與電子散射 (electron-electron scattering) 所造成, 而且元件退化隨著閘極測試電壓增加而增加, 當閘極測試電壓增加到與汲極測試電壓相等時, 這時元件的熱載子退化行為是單純由電子與電子散射所造成. 而電子與電子散射也會從基版電子與電子散射 (bulk electron-electron scattering) 轉變成表面電子與電子散射 (surface electron-electron scattering). 這種轉變是因為汲極電位的分布的轉變導致電流流向在中閘極電壓熱載子測試是位於基版, 而在高閘極電壓熱載子測試時電流是位於表面, 此外在本論文中也對於熱載子破壞位置隨著閘極測試電壓與測試時間的改變的變化作完整的探討.

Threshold voltage Vt extracted by gm-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in nitride spacer. The trapping of electrons in nitride spacer increases the series drain resistance, reducing the transconductance gm and the corresponding gate-to-source voltage Vgs at which peak gm occurs. It ultimately decreases the threshold voltage Vt extracted by the gm-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress, by considering the effect of series resistance on gm-maximum extrapolation method.
Spacer bottom oxide in the nitride spacer LDD device, which is used to prevent huge interfacial states between nitride and silicon interface, plays an important role in the hot carrier test. Because of the stress due to atomic size mismatch between nitride spacer and silicon, trap-assisted hot electron tunneling is more serious in nitride spacer LDD device than oxide spacer counterpart. Thicker bottom oxide can eliminate this effect. However, the optimized thickness of nitride spacer bottom oxide should be varied for different poly-silicon gate structure. The hot carrier stress in nitride spacer LDD device perform multi-stage degradation under Isub,max stress. It is dominated by electron trapping at the early stage, interfacial states (Nit) creation for the second stage, and self-limit hot carrier degradation at the last stage. The degradation for Ig,max stress in nitride spacer LDD devices is mostly contributed by electrons trapped in nitride/oxide interface.
The traditional hole traps and neutral electron traps caused by hot hole injection in low gate voltage stressing (Vgs = 1/5 Vds) no longer exist in ultra thin oxide (~ 2.0 nm) NMOS transistors. An electron injection is applied right after low gate voltage stress, however, there is neither enhanced hot carrier degradation nor “kink” existing in time-dependent increasing interfacial state ΔNit curve. Without hole traps, the damage of low-gate voltage stressed ultra thin oxide NMOS transistor is contributed by interfacial states Nit only. The bias range of interfacial states dominated only in hot carrier stressing is expanded from Vgs = 1/2 Vds to Vgs = 1/5 Vds, instead of the range which is around Vgs = 1/2 Vds for thicker oxide devices.
The simple guideline that use Isub change to determine the hot carrier damage type is no longer suitable in ultra-thin oxide device. Because only small portion of hot carrier damages located within pinch off region, in which the damage is not impacted device operation, the drain current degradation in saturation region is approaching to current degradation in linear region. It consequently increases substrate current degradation in low gate voltage. The smaller pinch off length is produced in ultra-thin oxide device because of scaling of drain operation voltage (1.2 V).
Hot carrier degradation in ultra-thin oxide device under medium gate voltage stress are contributed by both hot carrier impacted ionization and electron-electron scattering (EES). In medium gate voltage range, device degradation rate increases as gate voltage increase. It is contributed by the change of damage position toward LDD edge when gate voltage increases.
As ultra-thin oxide device under high gate voltage stress, surface EES dominates the hot carrier behavior and results in the worst device degradation. The change of bulk EES to surface EES is the results of potential difference between gate and drain, the squeeze potential of contour near drain edge is reduced as gate voltage increase. In high gate voltage stress, the self-limited hot carrier degradation occurred at the beginning of hot carrier stress. The defect location moves away from LDD edge as stress time increasing.

封面
摘要
誌謝
目錄
第一章 簡介
第二章 文獻回顧
第三章 氮化矽間隙壁N型金氧半電晶體早期熱載子測試中的臨界電壓值的萃取研究
第四章 深次微米氮化矽間隙壁輕?雜汲極N型金氧半電晶體早期熱載子退化行動
第五章 超薄氧化層N型金氧半電晶體在低閘極電壓熱載子測試中的退化行為
第六章 超薄氧化層N型金氧半電晶體在中閘極電壓熱載子測試中的退化行為
第七章 結論
英文附錄

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